Senior Async and IO Timing Methodology Engineer

NVIDIA has continuously reinvented itself over two decades. Our invention of the GPU in 1999 sparked the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. More recently, GPU deep learning ignited modern AI — the next era of computing. NVIDIA is a “learning machine” that constantly evolves by adapting to new opportunities that are hard to resolve, that only we can seek, and that matter to the world. This is our life’s work, to amplify human inventiveness and intelligence.

We are seeking a highly skilled Timing Methodology Engineer with expertise in asynchronous timing and I/O interface modeling to architect and deploy robust timing signoff practices across high-performance SoCs. You will play a critical role in defining cross-domain timing constraints, validating IO timing integrity, and enabling scalable STA methodologies across design hierarchies and technology nodes. We're looking for someone passionate about the challenges of designing most complex deep sub-micron design (3nm and beyond) who thrives on pushing the limits of precision and scalability. You’ll collaborate across teams to shape methodologies that influence the entire future of computing.

What you will be doing:

• Define and develop asynchronous timing closure methodologies, including safe handling of clock domain crossings (CDC), synchronization, and metastability analysis.

• Own and evolve I/O interface timing signoff, including external interface modeling (e.g., DDR, PCIe, LPDDR) and clock/data alignment constraints.

• Work closely with RTL and PD teams to extract clocking intent and drive accurate constraint generation from RTL and interface specifications.

• Create structural and timing checks for clock signal crossings across hierarchy, including isolation and level shifter timing.

• Build automated flows for STA constraint generation, coverage validation, and regression-based signoff using tools like PrimeTime or Tempus.

• Partner with package, signal integrity, and design teams to develop chip-to-package interface timing models.

• Support timing closure and signoff through timing audits, and silicon correlation.

What We Need To See:

• Bachelor's or Master's degree in Electrical Engineering or related field (or equivalent experience).

• 6+ years of experience in static timing analysis, methodology, or constraint development.

• Strong expertise in asynchronous timing, clock domain crossings, and I/O interface timing.

• Proficient in scripting (TCL, Perl, Python) for automation and flow development.

• Experience working with STA tools like Synopsys PrimeTime or Cadence Tempus.

• Deep understanding of clocking schemes, synchronizer structures, and constraint modeling for interface timing.

NVIDIA is widely considered to be the leader of AI computing, and one of the technology world’s most desirable employers. We have some of the most forward-thinking and hardworking people in the world working for us. If you're creative and autonomous, we want to hear from you.

Your base salary will be determined based on your location, experience, and the pay of employees in similar positions. The base salary range is 168,000 USD - 264,500 USD for Level 4, and 196,000 USD - 310,500 USD for Level 5.Applications for this job will be accepted at least until October 31, 2025.NVIDIA is committed to fostering a diverse work environment and proud to be an equal opportunity employer. As we highly value diversity in our current and future employees, we do not discriminate (including in our hiring and promotion practices) on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status or any other characteristic protected by law.