As the global leader in high-speed connectivity, Ciena is committed to a people-first approach. Our teams enjoy a culture focused on prioritizing a flexible work environment that empowers individual growth, well-being, and belonging. We’re a technology company that leads with our humanity—driving our business priorities alongside meaningful social, community, and societal impact.
Ciena’s next-generation Wavelogic Digital Signal Processor (DSP) programs rely on deep technical excellence, cross-functional collaboration, and continuous innovation. This role offers the opportunity to shape the frontend implementation of industryleading ASIC technology and contribute to the methodologies that keep Ciena at the forefront of highperformance optical networking.
How you will make an impact:
Execute frontend implementation for assigned IP subsystems, including synthesis, static timing analysis, logical equivalence checking, and clock domain crossing validation
Develop and maintain timing constraints to support synthesis and signoff for subsystem integration
Perform logical equivalence verification between Register Transfer Level (RTL) and gatelevel netlists throughout pre and postlayout stages
Validate clock domain crossings for toplevel ASIC integration to ensure functional integrity
Create and optimize scripts, tools, and documentation that improve synthesis and static timing workflows
Implement engineering change orders (ECOs) to support iterative design refinement
Collaborate closely with ASIC integration, IP development, physical design, and external Electronic Design Automation (EDA) partners to align frontend and backend implementation activities
The must haves:
B.Sc. in Electrical Engineering, Computer Engineering, or a related discipline (or equivalent experience)
Industry experience using synthesis and/or static timing analysis tools within an ASIC development environment
Knowledge of ASIC implementation flows, including synthesis, timing analysis, logical equivalence checking, and clock domain crossing validation
Familiarity with RTL design principles and hardware description languages
Ability to work effectively within multidisciplinary engineering teams and manage deliverables to project schedules
Nice to haves:
Experience with additional frontend or backend design activities such as floorplanning, Design for Testability (DFT), or place and route
Handson exposure to deepsubmicron ASIC technologies and advanced timing closure methodologies
Scripting experience (e.g., Python, Tcl, or similar) to enhance automation and debug workflows
Background supporting DSPcentric or highspeed ASIC development programs
Experience working with external EDA vendors or foundry technology teams
Pay Range:
The annual salary range for this position is $109,000 - $174,000 CAD.
Pay ranges at Ciena are designed to accommodate variations in knowledge, skills, experience, market conditions, and locations, reflecting our diverse products, industries, and lines of business. Please note that the pay range information provided in this posting pertains specifically to the primary location, which is the top location listed in case multiple locations are available.
Non-Sales employees may be eligible for a discretionary incentive bonus, while Sales employees may be eligible for a sales commission. In addition to competitive compensation, Ciena offers a comprehensive benefits package, including medical, dental, and vision plans, participation in 401(K) (USA) & DCPP (Canada) with company matching, Employee Stock Purchase Program (ESPP), Employee Assistance Program (EAP), company-paid holidays, paid sick leave, and vacation time. We also comply with all applicable laws regarding Paid Family Leave and other leaves of absence.
At Ciena, we are committed to building and fostering an environment in which our employees feel respected, valued, and heard. Ciena values the diversity of its workforce and respects its employees as individuals. We do not tolerate any form of discrimination.
Ciena is an Equal Opportunity Employer, including disability and protected veteran status.
If contacted in relation to a job opportunity, please advise Ciena of any accommodation measures you may require.
Skills Required
- B.Sc. in Electrical Engineering, Computer Engineering, or related discipline (or equivalent experience)
- Industry experience using synthesis and/or static timing analysis tools within an ASIC development environment
- Knowledge of ASIC implementation flows, including synthesis, timing analysis, logical equivalence checking, and clock domain crossing validation
- Familiarity with RTL design principles and hardware description languages
- Ability to work effectively within multidisciplinary engineering teams and manage deliverables to project schedules
- Experience with frontend or backend design activities such as floorplanning, DFT, or place and route
- Hands-on exposure to deep-submicron ASIC technologies and advanced timing closure methodologies
- Scripting experience (e.g., Python, Tcl) to enhance automation and debug workflows
- Background supporting DSP-centric or high-speed ASIC development programs
- Experience working with external EDA vendors or foundry technology teams
Ciena Compensation & Benefits Highlights
The following summarizes recurring compensation and benefits themes identified from responses generated by popular LLMs to common candidate questions about Ciena and has not been reviewed or approved by Ciena.
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Fair & Transparent Compensation — Pay is often characterized as competitive or above-market in certain roles and regions, with references to market-aligned salary ranges and transparency around pay bands.
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Healthcare Strength — Health coverage is frequently framed as comprehensive, including medical, dental, and vision, with indications that coverage can extend to dependents and is viewed as a meaningful component of total rewards.
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Leave & Time Off Breadth — Time-off offerings are described as flexible and generous, including Flex/uncapped PTO in many cases and additional paid time for volunteering.
Ciena Insights
What We Do
Ciena (NYSE: CIEN) is a global leader in networking systems, services, and software. We build the world’s most adaptive networks to enable our customers to deliver richer, more connected experiences for all users. At our core, Ciena is a company rooted in people. We prioritize deep, collaborative relationships within our teams and alongside our customers, partners, and communities around the world. For three-plus decades, we’ve brought our humanity to our relentless pursuit of innovation. We continue to lead the evolution of networking with a strong track record of industry firsts. As end-user expectations skyrocket, our customers and their networks must transform. Ciena powers this transformation by driving next-generation solutions built for maximum openness and agility—today and into the future. Corporate/Brand Values: • Customer First • Integrity • Velocity • Innovation • Outstanding People We're the perfect size for you to make an impact. W Only Ciena has the depth of expertise and the culture of collaboration and partnership required to help our partners evolve. We do this by strategically integrating hardware, services, and software in an open environment to ensure our clients’ networks are ‘fit for flexibility’ today and into the f
Why Work With Us
We are known for our industry-firsts, including the first coherent optical solution, converged packet-optical platform, and intelligence automation platform. Our commitment extends beyond innovation, logging in over 35,000 volunteer hours and $2 million to worthy causes in 2023. We're the perfect size and culture for you to make a difference.
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