Senior ASIC Design Verification Engineer

Posted 7 Days Ago
Be an Early Applicant
Milpitas, CA
130K-175K Annually
7+ Years Experience
Information Technology
The Role
Tarana Wireless is seeking a Senior ASIC Design Verification Engineer to work on verifying powerful SoCs for broadband wireless access. Responsibilities include defining verification strategies, building verification infrastructure, and collaborating with cross-functional teams. Required skills include System Verilog, UVM, C/C++, and experience in VLSI and SoC architecture. The salary range for this position is $130,000 to $175,000 with competitive benefits including medical, dental, vision, 401K match, and stock options.
Summary Generated by Built In


 

Do you think coding solves 99% of tech issues then this is the place for you in a highly collaborative environment. You will get to touch so many different UVM modules that you will make such an impact on our products. We are looking for someone that is self driven however knows when to collaborate to solve problems.  This position will verify the world’s most powerful SoCs for broadband wireless access that will connect the world wirelessly with fiber-class speed, on both Line of Sight and Non Line of Sight connections.

 

What you’ll be doing:

  • Work with some of the best DSP, system, and software engineers to define verification strategies and execute plans at system or full chip level
  • Build and continuously improve verification infrastructure and methodologies to meet the demands of next generation SoCs
  • Work with system architects, RTL designers, FPGA and emulation engineers to ensure that verification requirements and coverage are met for each project

 

Ways to stand out from the crowd:

  • Ability to handle complex and hard-do-solve problems in programming and verification
  • Ambitious and dedicated
  • Good interpersonal skills
  • Solid knowledge and strong experience of System Verilog, UVM, and C/C++
  • Experience with building abstraction layered and reusable verification testbench infrastructure
  • Working knowledge of scripting languages such as Python


Required Skills & Experience:

  • BSEE required/MSEE preferred
  • 5-12 years of experience 
  • Strong knowledge of UVM
  • Proficiency with at least one of these: C++, Object Oriented Programming, System Verilog
  • Strong knowledge on basic concepts of VLSI, SoC architecture
  • Ethernet and packet processing experience
  • Exceptional analytical skills and problem-solving skills

 

The salary range for this position is: $130,000 to $175,000
Compensation will be determined based on several factors including, but not limited to: skill set, years of experience and the employee’s geographic location.
Tarana provides competitive benefits to employees in this role including: Medical, dental and vision benefits, 401K match, flexible time off and stock option.
 

Top Skills

C/C++
System Verilog
The Company
HQ: Milpitas, California
432 Employees
On-site Workplace
Year Founded: 2009

What We Do

Tarana’s mission is to accelerate the deployment of fast, affordable internet access around the world. Through a decade of R&D and more than $400M of investment, the Tarana team has created a unique next-generation fixed wireless access (ngFWA) technology instantiated in its first commercial platform, Gigabit 1 (G1). It delivers a game-changing advance in broadband economics in both mainstream and underserved markets, using either licensed or unlicensed spectrum. G1 started production in mid-2021 and has since been embraced by more than 250 service providers in 19 countries and 41 US states.

Tarana is headquartered in Milpitas, California, with additional research and development in Pune, India. Visit our website for more on G1.

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