Senior Analog Mixed-Signal IC Layout Engineer

Reposted 2 Days Ago
Be an Early Applicant
Singapore
In-Office
Junior
Big Data • Information Technology
The Role
Design layout for advanced node CMOS products including floor planning and circuit integration while minimizing parasitic effects and ensuring compliance with EMIR and DRC rules.
Summary Generated by Built In

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions grounded in open standards. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. Discover more at www.asteralabs.com.

The company seeks a highly motivated and team-oriented individual to work with both layout and design engineers across multiple time zones

As an Integrated Circuit Designer, you will be part of a key team designing and developing sophisticated advanced node CMOS products.

Key Job Duties:

  • The design and development of the layout for integrated circuits according to electronics engineering principles, using software to create design schematics and diagrams. This will include [floor planning, creating layouts of building blocks and integrating layouts for circuits such as PLL, DLL, ADC, regulators, amplifiers, TX, RX, and CDRs in advanced CMOS nodes. Your focus will include minimizing parasitic and skew, matching, EMIR, and antenna rules on top of DRC and LVS]
  • The management of manufacturing process of the products, including technology yield and performance of the products. 
  • The development of test programmes and procedures to ensure the products meet their performance specifications.
  • The provision of advice on aspects of semiconductor process technology and maintain and repair semiconductor process equipment.

Basic Qualifications:

  • At least a bachelor’s degree in electrical engineering

Required Experience:

  • 2+ years of experience in the development of layouts for highspeed analog IC designs in finFET technology.
  • Experience with layout extraction tools and to analyzing layout parasitic to achieve high quality layout for highspeed circuits.
  • EMIR and antenna DRC rules aware layout practices.
  • Experience writing SKILL and TCL scripts is highly recommended

We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.

Top Skills

Cmos
Skill
Tcl
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The Company
HQ: Santa Clara, CA
148 Employees
Year Founded: 2017

What We Do

Astera Labs Inc., a fabless semiconductor company headquartered in the heart of California’s Silicon Valley, is a leader in purpose-built connectivity solutions for data-centric systems throughout the data center.

Partnering with leading processor vendors, cloud service providers, seasoned investors, and world-class manufacturing companies, Astera Labs is helping customers remove performance bottlenecks in data-intensive systems that are limiting the true potential of applications such as artificial intelligence and machine learning.

The company’s product portfolio includes system-aware semiconductor integrated circuits, boards, and services to enable robust CXL, PCIe, and Ethernet connectivity.

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