Senior Analog Layout Engineer

Lumai's accelerator depends on custom analog and mixed-signal silicon - data converters, bias and reference circuits, clocking - designed and laid out in house. That effort is scaling up in Spain, and layout is where a good circuit either survives silicon or quietly stops working. This hire owns it.

You will own the physical implementation of Lumai's custom analog and mixed-signal blocks, from data converters to bias and clocking circuits, on advanced CMOS process nodes. You will translate schematic intent into silicon-accurate layout in tight feedback loops with circuit designers, and you will be the team's authority on matching techniques, parasitic-sensitive floorplanning and the physical verification flows that get a design tapeout-ready. You will report to the Senior Analog/Mixed-Signal Design Lead.

What is genuinely hard about this is that layout is where matching, parasitics and noise coupling decide whether the circuit that was designed is the circuit that comes back. The work is iterative and evidence-driven: extraction and back-annotated simulation cycles to close margins, and DRC, LVS and ESD sign-off where a violation found late is expensive.

By month six, you will have taken blocks through the full sign-off flow to tapeout-ready, documented the matching standards and layout review practice you want the team to hold, and started mentoring junior layout engineers as the team grows.

• Own full-custom layout of analog and mixed-signal blocks: data converters, bias and reference circuits, PLLs and analog front-end IP.

• Apply the matching technique each block needs - common-centroid placement, dummy structures, guard rings and symmetric routing - to preserve circuit performance in silicon.

• Identify and mitigate parasitic-sensitive risks including coupling, IR drop and substrate noise, working with circuit designers on back-annotated simulation.

• Drive parasitic extraction and back-annotated simulation cycles to close performance margins before tapeout.

• Own DRC, LVS and ESD/latch-up sign-off for assigned blocks, resolving violations with the PDK and foundry liaison team.

• Contribute to block and sub-system floorplanning, balancing area, routing congestion and noise isolation.

• Mentor junior layout engineers on matching techniques and advanced-node layout rules.

• Support post-silicon debug by correlating layout-dependent effects with bench characterisation findings.

• Seven or more years of custom analog/mixed-signal layout experience on advanced CMOS process nodes (16nm/12nm class or below).

• Deep hands-on expertise in matching techniques for precision analog circuits: common-centroid placement, dummy structures and symmetric routing.

• A strong track record on parasitic-sensitive layout: identifying and mitigating coupling, substrate noise and IR drop.

• Proficiency with the Cadence Virtuoso layout suite and its DRC, LVS and PEX flows.

• Experience taking layout from floorplan through DRC/LVS sign-off and tapeout on at least one production design.

• Layout experience specific to data converters (capacitor arrays, current source arrays) or high-speed clocking structures.

• Exposure to ESD and ISO/automotive-grade reliability layout requirements.

• Experience mentoring or leading a small layout team.

• Familiarity with photonics or optical-electronic co-packaged layout considerations.

Lumai is the optical compute company building the next generation of AI infrastructure. Spun out of optics research at the University of Oxford in 2021, we compute with light instead of electrons. Our 3D optical technology carries out the matrix multiplications at the heart of AI inside beams of light travelling through free space, which lets it go beyond the limits of both silicon GPUs and integrated photonics.

In April 2026 we launched Iris Nova, the world's first optical computing system to run billion-parameter large language models in real time, using up to 90% less energy than conventional GPU-based systems. Iris Nova, the first server in the family, is now available for evaluation by hyperscalers, neoclouds, enterprises and research institutions. Aura and Tetra will follow.

Our work won the Falling Walls Award for Science Breakthrough of the Year 2025 and 'Best Overall Technology' at the OCP Future Technologies Symposium. We are headquartered in Oxford.

You'll work on a new kind of computer. Optical computing for AI has been promised for decades. We have a working system running real models, and the hard part left is taking it to volume.

Your work ships. We are moving from first product to volume production, so what you build this year goes into the servers our customers run.

You'll work across disciplines. Optical engineers, machine learning researchers, and hardware and software engineers solve problems together. You will learn things that don't appear on your job description.

The work matters beyond Lumai. AI's appetite for energy is one of the defining constraints of the next decade. Our mission is sustainable intelligence at global scale: AI that is faster, cheaper to run and far less power-hungry.

You'll join early. You'll have a real say in how we build the product, the team and the way we work.

Lumai is an equal opportunity employer. We make hiring decisions based on skills, experience and potential, and we welcome applications from people of all backgrounds. If you need an adjustment at any stage of the hiring process, let us know and we will do our best to support you.