Senior Analog Design Engineer

Posted Yesterday
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San Diego, CA, USA
In-Office
115K-145K Annually
Senior level
Semiconductor • Manufacturing
The Role
Design, simulate, and optimize high‑speed, precision CMOS analog circuits for ATE products. Perform layout, verification, and post‑layout simulation (Monte Carlo, SOAC, corners). Support mixed‑signal channel/chip simulation, IC characterization, test development, and qualification while collaborating with digital, layout, test, and applications teams.
Summary Generated by Built In

At Elevate Semiconductor, we empower semiconductor and system test customers by creating world class ICs that tackle the industry’s most complex automated test equipment challenges. Our innovative team designs the lowest power, highest density solutions to reduce cost of test while pushing performance forward.

As a Senior Analog Design Engineer, you will contribute to the design and optimization of analog circuits used in high performance ATE products. You will work closely with cross functional teams and take ownership of circuit blocks from concept through silicon validation.

This role is based in San Diego, CA and requires the individual to be onsite five days per week.

Responsibilities

  • Design and simulate schematics for a variety of high speed and precision CMOS ATE circuits
  • Perform layout, verification, and post layout simulation including Monte Carlo, SOAC, and corner analysis
  • Participate in mixed signal simulation at the channel and chip levels
  • Develop circuit architectures with a focus on power, performance, and density optimization
  • Support IC characterization, test development, and qualification activities
  • Collaborate with internal teams including digital design, layout, test, and applications

Requirements

  • Bachelor’s degree in electrical engineering; Master’s degree preferred
  • 5-8 years of professional experience in analog IC design
  • Strong foundation in analog CMOS circuit design
  • Experience designing and analyzing feedback loops including stability and compensation
  • Solid understanding of the full IC design, qualification, and manufacturing cycle
  • Hands on experience with analog and mixed signal EDA tools such as Cadence, Mentor Graphics, or Tanner
  • Experience with LVS and DRC using Cadence or Mentor tools

Benefits
  • 100% Employer Paid Health Insurance (Medical, Dental, Vision)
  • Unlimited Paid Time Off
  • Performance Bonuses
  • Free Lunch Catered in by Local Restaurants
  • Private Equity Options
  • Retirement Plans
  • Sabbatical Program
  • Tuition Reimbursement
  • Volunteer Days
  • Relocation Assistance
  • Conference Attendance Support
  • Biweekly Phone Stipend
  • Employee Assistance Program

The salary range for this role is $115,000.00-$145,000.00. Starting salary will be aligned with your relevant experience and demonstrated capabilities during the interview process. Typically, candidates begin at the initial tier of our compensation range, with placement adjusted for candidates presenting extensive directly applicable experience.

Skills Required

  • Bachelor's degree in Electrical Engineering
  • Master's degree in Electrical Engineering
  • 5-8 years of professional experience in analog IC design
  • Strong foundation in analog CMOS circuit design
  • Experience designing and analyzing feedback loops including stability and compensation
  • Solid understanding of the full IC design, qualification, and manufacturing cycle
  • Hands-on experience with analog and mixed-signal EDA tools such as Cadence, Mentor Graphics, or Tanner
  • Experience with LVS and DRC using Cadence or Mentor tools
  • Ability to be onsite in San Diego, CA five days per week
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The Company
HQ: Phoenix, AZ
34 Employees

What We Do

ElevATE is a leading supplier of innovative, low power, high density components for the design of next generation Automated Test Equipment (ATE). With a proven track record of consistently delivering the highest density, lowest power solutions available, systems designed around ElevATE products have a competitive advantage in the ATE market space and are able to adapt successfully to emerging trends and challenges while providing ever increasing end user value. ElevATE offers a wide variety of solutions for the ATE market with variable levels of integration so that we can serve the unique requirements of multiple end user segments such as System on a Chip (SOC) Test, Memory Test, Test During Burn-in (TDBI), In-Circuit Test (ICT) and beyond. ElevATE was founded in June, 2012 by the former members of the Intersil ATE product line. Our founders have over 100 years of combined ATE experience while supporting roles directly related to ATE at companies like Brooktree Corp, Edge Semiconductor, Semtech, Megatest, Nextest, Maxim, and Planet ATE. This broad knowledge base and experience enables ElevATE to provide focused support that caters to the unique requirements of the ATE market.

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