The Group
Intel's Advanced Design Foundational IP Organization (AD-FIP) within Design Technology Platform (DTP) drives pathfinding and development of the analog/mixed-signal and high-speed I/O IP that defines what Intel's leading-edge process technologies can deliver. The High-Speed I/O team develops SerDes and die-to-die interface reference designs and test chips that co-optimize Intel process technology with next-generation wireline standards, including high-speed PAM4 electrical links, PCIe, UCIe, and HBM.
The Role
We are seeking a senior technical expert in high-speed SerDes circuit design and SerDes system architecture. You will own SerDes link architecture on Intel's leading technology test chips, from link budget and equalization strategy down to transistor-level design of the critical analog front-end and clocking blocks. You will also translate link requirements into device, interconnect, and design-rule requirements that shape future Intel process nodes. This is a senior individual-contributor role with technical leadership across design, layout, and measurement engineers.
Responsibilities
- Define SerDes link architecture for next-generation interfaces (224G/448G-class PAM4 electrical links, PCIe Gen7/Gen8, UCIe): channel analysis, link budget, jitter and noise budgeting, and equalization partitioning across TX FFE, RX CTLE, DFE, and ADC/DSP-based receivers.
- Build and maintain system-level link models (statistical and time-domain, in MATLAB or Python; COM and IBIS-AMI based) and use them to derive block-level specifications for TX, RX, ADC, and clocking circuits.
- Lead transistor-level design of critical SerDes blocks: TX drivers (SST/CML) with FFE, RX AFE (CTLE, VGA, termination, T-coil and ESD co-design), DFE and slicers, time-interleaved ADC front ends, CDR and phase interpolators, LC and ring PLLs, and clock distribution.
- Drive test-chip definition, integration, tapeout readiness, and silicon bring-up; correlate measured BER, eye, jitter, and power against models, and lead root-cause analysis of silicon-to-model gaps.
- Translate SerDes requirements into process and PDK requirements (device fT/fmax and parasitics, BEOL RC, inductor Q, matching, ESD capacitance budget, reliability and aging) and drive design-technology co-optimization with process, PDK, and template-library teams.
- Provide technical leadership: mentor engineers, lead design reviews, and represent Intel Foundry in technical engagements with IP partners and foundry customers.
You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the requirements and are considered a plus factor in identifying top candidates.
Minimum Qualifications
- Bachelors Degree in Electrical Engineering, Computer Engineering, or Electrical and Computer Engineering with 6+ years of industry experience in high-speed wireline SerDes circuit design experience -OR- Master's degree in Electrical Engineering, Computer Engineering, or Electrical and Computer Engineering with 4+ years of industry experience in high-speed wireline SerDes circuit design, -OR- Ph.D. in Electrical Engineering, Computer Engineering, or Electrical and Computer Engineering with 2+ years of industry experience in high-speed wireline SerDes circuit design.
- Experience in Transistor-level design of SerDes TX, RX, or clocking circuits in at least one silicon-proven design at 28 Gb/s per lane or higher.
- Experience in at least one of the following:
- SerDes link architecture: channel and link-budget analysis or equalization trade-off studies used to set block-level specifications.
- Lab validation of high-speed links: BER, eye, or jitter measurement and correlation to simulation.
- Behavioral or statistical link modeling in MATLAB or Python.
Preferred Qualifications
- Experience with Silicon-proven designs at 56 Gb/s PAM4 or higher, in FinFET or GAA CMOS; multiple tape-outs with block ownership.
- Experience across all three areas above (architecture, lab validation, and link modeling).
- Experience in ADC/DSP-based receivers at 112 Gb/s PAM4 or higher, including time-interleaved ADC design. - 224 Gb/s-class link development (IEEE 802.3dj, OIF CEI-224G). - PCIe Gen6/Gen7 PHY or UCIe die-to-die PHY development.
- Design experience on 5nm-class or more advanced nodes, with design-technology co-optimization experience with process teams.
- Experience in package and channel co-design: package/PCB channel modeling, signal and power integrity, crosstalk.
- Experience with first-author publications at ISSCC, VLSI Symposium, CICC, or JSSC; patents in SerDes circuits or architecture.
- Technical leadership of a multi-engineer SerDes design team through a full PHY delivery.
Take the next step to make an impact at Intel. Join us in redefining possibilities, driving innovation, and shaping the future of technology.
Job Type:Experienced HireShift:Shift 1 (United States of America)Primary Location: US, Oregon, HillsboroAdditional Locations:US, California, Santa ClaraPosting Statement:All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.Position of TrustN/ABenefits
We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel.
Annual Salary Range for jobs which could be performed in the US: $141,910.00-269,100.00 USD
The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.
Work Model for this Role
This role will require an on-site presence. * Job posting details (such as work model, location or time type) are subject to change.*
ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.Skills Required
- Bachelor’s degree in Electrical Engineering, Computer Engineering, or Electrical and Computer Engineering with 6+ years of industry experience in high-speed wireline SerDes circuit design
- Master’s degree in Electrical Engineering, Computer Engineering, or Electrical and Computer Engineering with 4+ years of industry experience in high-speed wireline SerDes circuit design
- Ph.D. in Electrical Engineering, Computer Engineering, or Electrical and Computer Engineering with 2+ years of industry experience in high-speed wireline SerDes circuit design
- Transistor-level design experience with SerDes TX, RX, or clocking circuits in at least one silicon-proven design at 28 Gb/s per lane or higher
- Experience with SerDes link architecture, including channel and link-budget analysis or equalization trade-off studies used to set block-level specifications
- Experience with lab validation of high-speed links, including BER, eye, or jitter measurement and correlation to simulation
- Experience with behavioral or statistical link modeling in MATLAB or Python
- Silicon-proven designs at 56 Gb/s PAM4 or higher in FinFET or GAA CMOS, with multiple tape-outs and block ownership
- Experience across SerDes architecture, lab validation, and link modeling
- Experience with ADC/DSP-based receivers at 112 Gb/s PAM4 or higher, including time-interleaved ADC design
- Experience with 224 Gb/s-class link development, IEEE 802.3dj, or OIF CEI-224G
- PCIe Gen6/Gen7 PHY or UCIe die-to-die PHY development experience
- Design experience on 5nm-class or more advanced nodes and design-technology co-optimization experience with process teams
- Package and channel co-design experience, including package/PCB channel modeling, signal and power integrity, and crosstalk
- First-author publications at ISSCC, VLSI Symposium, CICC, or JSSC, or patents in SerDes circuits or architecture
- Technical leadership of a multi-engineer SerDes design team through full PHY delivery
Intel Compensation & Benefits Highlights
The following summarizes recurring compensation and benefits themes identified from responses generated by popular LLMs to common candidate questions about Intel and has not been reviewed or approved by Intel.
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Leave & Time Off Breadth — Sabbaticals and paid time off are highlighted as signature elements, with an established program offering four weeks after four years or eight weeks after seven years. This distinctive time off is positioned as a meaningful part of the overall package.
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Parental & Family Support — Paid bonding leave of 12 weeks and a New Parent Reintegration program, plus fertility benefits around $40,000 and up to $15,000 adoption reimbursement with no lifetime cap, are clearly stated. These programs are presented as standout components alongside broader family support resources.
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Healthcare Strength — Multiple medical plan options with 2026 updates, a shift to Spring Health for EAP, and in‑network virtual medical visits covered at 100% beginning in 2026 indicate a comprehensive offering. These features signal an emphasis on robust medical access and mental health support.
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