ASIC Design and Verification Engineer - AI

About Analog Devices

Analog Devices, Inc. (NASDAQ: ADI ) is a global semiconductor leader that bridges the physical and digital worlds to enable breakthroughs at the Intelligent Edge. ADI combines analog, digital, and software technologies into solutions that help drive advancements in digitized factories, mobility, and digital healthcare, combat climate change, and reliably connect humans and the world. With revenue of more than $9 billion in FY24 and approximately 24,000 people globally, ADI ensures today's innovators stay Ahead of What's Possible™. Learn more at www.analog.com and on LinkedIn and Twitter (X).

This position is in the Engineering Enablement (EE) group that provides industry-leading tools, methodologies, and support to accelerate product development across the company. You’ll be a part of the Systems Verification and Validation (SVV) team within the EE organization in ADI’s Vertical Business Units. SVV is responsible for developing, adopting, and supporting tools, methodologies, and solutions across the entire design verification landscape - including Unified Metric-Driven Verification (MDV), System Verilog (SV)/UVM-based methodologies, Mixed-Signal DV, Post-Silicon Validation Shift-Left, Formal Verification, Functional Safety, Security, Portable Stimulus, and Emulation/Prototyping technologies.

A major focus of the group recently has been around deploying and integrating advanced Agentic AI methods to boost productivity in areas of digital architecture, digital design, digital implementation DV and embedded software. This role offers an exciting opportunity to contribute to rapid advancements in a dynamic and fast-evolving field filled with engaging challenges.  

About the Role

In this role, you will leverage your knowledge in Integrated Circuit (IC) design and verification with working knowledge of AI/ML to develop, integrate, deploy, and support best-in-class Agentic AI solutions including custom instructions, skills and automation scripts. You will help connect these tools with multiple engineering domains including system architecture, design, verification, and software teams to enhance productivity and quality. This is not an Agentic AI role, though you will use/create agents to accelerate output.

Key Responsibilities

• Evaluate and integrate Agentic AI tools with industry standard and proprietary tools and workflows for massively accelerating various parts of the IC design and verification lifecycle
• Develop libraries of custom instructions, skills, and automation scripts for Agentic AI tools
• Apply machine learning and agentic AI techniques to extend and enhance ADI’s EDA tools
• Connect APIs and SDKs to ADI’s design databases
• Educate users on best practices for using Agentic AI tools, create documentation and deliver training workshops
• Work closely with digital and analog design engineers, verification experts, and tool developers to identify pain points and integrate AI solutions
• Evaluate and benchmark emerging AI/ML tools for semiconductor workflows
• Develop and maintain automation tools to improve verification productivity and debug efficiency
• Keep abreast of the latest in generative AI and agentic frameworks

Required Qualifications

• 5 years of experience in the IC design and verification domain
• Experience with LLM-related techniques: prompt engineering, RAG, vector databases
• Strong experience with scripting languages (Python, Bash)
• Strong experience with System Verilog/UVM and C-based test bench development
• Proficiency with git version control and CI/CD pipelines (GitHub Actions, Jenkins)
• Strong command-line Linux skills and experience with common Linux utilities
• Excellent debugging and analytical skills
• Strong coding and documentation practices
• Excellent communication skills to work across teams

Preferred Qualifications

• Knowledge of AI Infrastructure development, including MCP integration
• API integration experience (REST/GraphQL)
• Familiarity with cloud platforms (AWS, Azure) and CI/CD practices for ML tools
• Experience fine-tuning or training LLMs for domain-specific applications
• Experience with synthesizable RTL development
• Experience with debugging of RTL and gate simulations
• Experience with Xcelium and Synopsys tools
• Proficiency in Formal Verification techniques and tools
• Experience with coverage-driven verification methodologies
• Familiarity with low power verification (UPF)

Preferred Education

• Bachelor's or master's degree in electrical engineering, Computer Engineering, or equivalent experience

For positions requiring access to technical data, Analog Devices, Inc. may have to obtain export  licensing approval from the U.S. Department of Commerce - Bureau of Industry and Security and/or the U.S. Department of State - Directorate of Defense Trade Controls.  As such, applicants for this position – except US Citizens, US Permanent Residents, and protected individuals as defined by 8 U.S.C. 1324b(a)(3) – may have to go through an export licensing review process.

Analog Devices is an equal opportunity employer. We foster a culture where everyone has an opportunity to succeed regardless of their race, color, religion, age, ancestry, national origin, social or ethnic origin, sex, sexual orientation, gender, gender identity, gender expression, marital status, pregnancy, parental status, disability, medical condition, genetic information, military or veteran status, union membership, and political affiliation, or any other legally protected group.

EEO is the Law: Notice of Applicant Rights Under the Law.

• Actual wage offered may vary depending on work location, experience, education, training, external market data, internal pay equity, or other bona fide factors.

• This position qualifies for a discretionary performance-based bonus which is based on personal and company factors.

• This position includes medical, vision and dental coverage, 401k, paid vacation, holidays, and sick time, and other benefits.