Lead Digital Design Engineer

We are at a pivotal moment in the semiconductor industry. Technology is evolving at an unprecedented pace, and Texas Instruments' MCU organization is right at the center of this transformation.

Our current work is focused on developing solutions for high-growth markets — including AI-driven data centers and emerging domains such as humanoid systems. These areas are actively shaping the future of computing, automation, and intelligent systems, offering a rare opportunity to work on cutting-edge technologies with real-world, large-scale impact.

If you are passionate about solving complex technical challenges and want to contribute to innovations in these fast-growing segments, this is your moment. This role is not only technically rewarding — it is strategically significant.

Texas Instruments is seeking an experienced and driven DFT Lead to lead and shape the test engineering strategy within our MCU organization. In this role, you will direct and guide the activities of a research and technical design function responsible for designing, developing, modifying, and evaluating digital electronic parts, components, and integrated circuitry for electronic equipment and hardware systems.

You will play a critical leadership role in ensuring that our silicon is not only designed for performance and power efficiency, but also for testability, reliability, and manufacturability — qualities that are essential as we scale into AI and next-generation compute platforms.

Responsibilities :

• Lead a SoC Front End (FE) team to own SoC integration of a complex ARM architecture based SoC upto RTM
• Collaborate with systems, IP and DV teams to align on feature updates, IP deliverables and ensure timely SoC integration catering to Product Requirements
• Interact and engage with SoC system architect and ensure functional, performance, safety and security requirements are fully comprehended
• Work with backend, DFT team, flow teams to come up with SoC releases
• Point of contact person to IP team from SoC perspective, key member to drive integration reviews and participate in DV reviews to give feedback
• Drive complete SoC integration, LEC, LINT checks and CDC/RDC analysis to ensure high quality deliverables
• Responsible for ensuring power intent of the SoC is understood and implemented correctly through Low-Power checks like CLP

Qualifications :

• Educational requirement Bachelor or Masters in EE/ECE/CS or related specializations with 5+ years of experience in SoC/subsystem design/integration

Skills :

• Experience with integration of SoC and sub-systems
• Well experienced with analysis and understanding of system level use case scenarios, safety and security requirements etc
• Experience with SoC power analysis and power optimization
• Strong experience with advanced low power design techniques
• Good understanding of constraints development for Physical Design implementation / Static Timing Analysis
• Good understanding of SoC Debug architectures, Design-for-Debug, Design-for-Test will be highly desirable.
• Effective communication skills to interact with all stakeholders.
• Must be highly focused and remain committed to obtaining closure on project goals
• Passionate about mentoring and developing people in their careers