RELIABILITY LTE ENGINEER

Job Description:

• Develop Reliability biasing stress board for NPI/NTI products align with JEDEC and customer specification.

• Cooperate with multinational product development team including Design and Quality and work with external manufacturers on board fabrication

• Develop program in C language with new product development team for reliability stress

• Validate device on bench and reliability stress equipment to ensure device operation stability and provide final validation report.

• Debug and troubleshoot on failure DUT, board, equipment & machine using various tools such as thermal imaging camera & oscilloscope

• Work with cross department team including Failure Analysis & Business Line to analyze qualification failure using 8D methodology, FMEA, Fault Tree Analysis, & 3x5 Why tools.

• Provide guidance to technician on biasing execution procedure and sustaining activities related to reliability biasing boards.

Requirement:  

•  Bachelor’s degree in Electrical and Electronics Engineering or equivalent.

•  3-5 years’ experience in semiconductor reliability assessment field are preferred.

• Knowledge in PCB fabrication, schematic, & layout.

• Good programming knowledge (C language).

• Experience with embedded system will be an added value.

• Experience with life test reliability equipment & methodology will be an added value (HTOL, HAST, THB)

Note: Fresh Graduates are encouraged to apply. Grade level will be based on skills and experience. Only short-listed candidates will be notified 

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