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Job Description:As part of TLR team (top-level-route), R&D Engineer is primarily responsible for :-
1) Place and Route, CTS, Routablity analysis with respect to congestion.
2) Well versed in physical verification aspect, DRC, LVS, Antenna, LUP, ( chip finishing and Tapeout)
3) Integration of analog blocks, Meeting RC requirements for manual/special signals
4) Good understanding of calibre rule deck of DRC/LVS/DFM,DFY, ERC and ESD latchup.
5) Responsible for all the integrity checks and post Tapeout eJob view release,
6) Good scripting knowledge perl and TCL, familiar with caliber, Innovus,
7) Understanding of VLSI fabrication process,
8) Implementing timing ECOs. Implementing IR drop fixes, SPEF/GPD extraction, signal EM fixes, Noise analysis.
9) Responsible for all the integrity checks and post Tapeout eJob view.
10) Open to new responsibilities in context of rapid technological change.
11) Good communication skills, work closely with the team members to accomplish PD milestone.
12) Secondary competencies :- Good understanding of CTS, STA, PTSI and timing.
Relevant experience of CAD tools cadence Innovus, Calibre is preferred.
Experiance 4 to 8 years
Broadcom is proud to be an equal opportunity employer. We will consider qualified applicants without regard to race, color, creed, religion, sex, sexual orientation, national origin, citizenship, disability status, medical condition, pregnancy, protected veteran status or any other characteristic protected by federal, state, or local law. We will also consider qualified applicants with arrest and conviction records consistent with local law.
If you are located outside USA, please be sure to fill out a home address as this will be used for future correspondence.
Skills Required
- 4 to 8 years relevant experience
- Place and Route, CTS, routability analysis and congestion optimization
- Physical verification experience: DRC, LVS, Antenna checks, LUP (chip finishing and tapeout)
- Integration of analog blocks and meeting RC requirements for manual/special signals
- Understanding of Calibre rule decks for DRC/LVS/DFM, DFY, ERC and ESD latchup
- Post-tapeout integrity checks and eJob view release responsibility
- Scripting proficiency in Perl and TCL
- Familiarity with Cadence Innovus and Calibre CAD tools
- Understanding of VLSI fabrication process
- Implementing timing ECOs, IR drop fixes, SPEF/GPD extraction, signal EM fixes and noise analysis
- Good communication skills and ability to work closely with team to meet PD milestones
- Secondary: strong understanding of CTS, STA, PTSI and timing
Broadcom Compensation & Benefits Highlights
The following summarizes recurring compensation and benefits themes identified from responses generated by popular LLMs to common candidate questions about Broadcom and has not been reviewed or approved by Broadcom.
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Equity Value & Accessibility — Equity is used broadly through RSUs with quarterly or annual vesting, and an ESPP with a discount and look‑back that can add meaningful upside. Company disclosures show ongoing equity grants, including inducement RSUs tied to acquisitions, underscoring equity’s central role in total rewards.
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Retirement Support — A 401(k) plan with a competitive company match and immediate vesting is consistently highlighted, supporting long‑term savings. Tax‑advantaged accounts like HSA/FSA further strengthen the financial wellness toolkit.
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Pay Growth & Progression — Compensation ceilings in technical tracks are described as high, with wide ranges and very strong totals for experienced engineers. Sales compensation is also characterized as competitive, supporting attractive on‑target earnings.
Broadcom Insights
What We Do
Broadcom Inc. (NASDAQ: AVGO) is a global technology leader that designs, develops and supplies semiconductor and infrastructure software solutions.
