R&D Engineer IC Design 4

Posted 2 Days Ago
Be an Early Applicant
2 Locations
In-Office
122K-195K Annually
Senior level
Software • Semiconductor • Manufacturing
The Role
Design and verify front-end RTL blocks for ASIC cores: define architecture, implement logic, perform synthesis, constraints, simulation and formal verification, analyze timing from physical implementation, debug Verilog designs, and collaborate across global teams within the full ASIC implementation flow.
Summary Generated by Built In

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Job Description:

You will be responsible for the front end design and verification of design blocks for these cores. Specific duties will include, but are not limited to architecture definition, logic design, synthesis, constraint development; design verification through simulation, formal verification, along with analysis of timing from the physical implementation. You will design logic blocks from systems requirements documents and will simulate and debug designs with Verilog simulation. Familiarity with entire ASIC design and implementation flow.

·        Ability to work independently as well as part of a large team spanning multiple geographies.

·        Education: BS/MS in Electrical or Computer Engineering or equivalent

· Bachelors and 8+ years of related experience; or Masters degree and 6+ years of related experience

·        Experience with complete ASIC or standard product implementation flow from RTL synthesis, timing analysis / closure.

·        Requires proficiency with the following design tools / flows:

·         TCL/Perl scripting

·         Synthesis experience with either Synopsys Design Compiler/ DC topo or Cadence RTL compiler

·         Timing analysis experience with Primetime for high frequency designs and advanced technology nodes/libraries

·         Understanding of liberty LIB models for timing

·         Formal verification (Synopsys Formality / Cadence Conformal)

·         Spyglass Lint

·         Power analysis of RTL and gate level netlists

·         Familiarity with DFT (design for test) and scan methodology

·         Version control (svn, git, etc)


Compensation and Benefits


The annual base salary range for this position is USD 121,900.00 To USD 195,000.00

As a valued member of our team, you'll be eligible for a discretionary annual bonus and the opportunity to receive not only a competitive new hire equity grant, but also annual equity awards, connecting your success directly to the company's growth. All subject to relevant plan documents and award agreements.


Broadcom offers a competitive and comprehensive benefits package: Medical, dental and vision plans, 401(K) participation including company matching, Employee Stock Purchase Program (ESPP), Employee Assistance Program (EAP), company paid holidays, paid sick leave and vacation time. The company follows all applicable laws for Paid Family Leave and other leaves of absence.


Broadcom is proud to be an equal opportunity employer.  We will consider qualified applicants without regard to race, color, creed, religion, sex, sexual orientation, national origin, citizenship, disability status, medical condition, pregnancy, protected veteran status or any other characteristic protected by federal, state, or local law.  We will also consider qualified applicants with arrest and conviction records consistent with local law.


If you are located outside USA, please be sure to fill out a home address as this will be used for future correspondence.

Skills Required

  • BS/MS in Electrical or Computer Engineering or equivalent
  • Bachelors with 8+ years related experience or Masters with 6+ years related experience
  • Ability to work independently and as part of a geographically distributed team
  • Familiarity with entire ASIC design and implementation flow
  • Experience with RTL synthesis and complete ASIC/standard product implementation flow, including timing analysis/closure
  • Proficiency with TCL and Perl scripting
  • Synthesis experience with Synopsys Design Compiler / DC topo or Cadence RTL Compiler
  • Timing analysis experience with Synopsys PrimeTime for high frequency designs and advanced nodes
  • Understanding of Liberty (LIB) timing models
  • Formal verification experience (Synopsys Formality or Cadence Conformal)
  • Static linting experience with SpyGlass
  • Power analysis of RTL and gate-level netlists
  • Familiarity with DFT and scan methodology
  • Version control experience (SVN, Git)
  • Experience simulating and debugging designs with Verilog simulation

Broadcom Compensation & Benefits Highlights

The following summarizes recurring compensation and benefits themes identified from responses generated by popular LLMs to common candidate questions about Broadcom and has not been reviewed or approved by Broadcom.

  • Equity Value & Accessibility Equity is used broadly through RSUs with quarterly or annual vesting, and an ESPP with a discount and look‑back that can add meaningful upside. Company disclosures show ongoing equity grants, including inducement RSUs tied to acquisitions, underscoring equity’s central role in total rewards.
  • Retirement Support A 401(k) plan with a competitive company match and immediate vesting is consistently highlighted, supporting long‑term savings. Tax‑advantaged accounts like HSA/FSA further strengthen the financial wellness toolkit.
  • Pay Growth & Progression Compensation ceilings in technical tracks are described as high, with wide ranges and very strong totals for experienced engineers. Sales compensation is also characterized as competitive, supporting attractive on‑target earnings.

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The Company
HQ: Palo Alto, CA
38,985 Employees
Year Founded: 1991

What We Do

Broadcom Inc. (NASDAQ: AVGO) is a global technology leader that designs, develops and supplies semiconductor and infrastructure software solutions.

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