Quantum Topological Qubit Lead Integrator

About GlobalFoundries

GlobalFoundries is a leading full-service semiconductor foundry providing a unique combination of design, development, and fabrication services to some of the world’s most inspired technology companies. With a global manufacturing footprint spanning three continents, GlobalFoundries makes possible the technologies and systems that transform industries and give customers the power to shape their markets. For more information, visit www.gf.com.

Introduction

The Topological Qubit Lead Integrator is a senior technical and organizational leadership role within the Quantum Technology Solutions organization. This role is responsible for integrating the semiconductor building blocks required for scalable topological qubit platforms, spanning advanced materials, device architectures, BEOL integration, and heterogeneous assembly. The position combines deep technical leadership with program execution, guiding multidisciplinary teams to translate emerging topological quantum technologies into manufacturable, scalable hardware solutions.

Summary of Role

The Topological Qubit Lead Integrator owns the end-to-end semiconductor integration strategy for topological qubit systems. This includes aligning advanced materials (III‑V heterostructures, superconductors, and topological materials), device architectures, BEOL interconnect technologies, and 3D heterogeneous integration into manufacturable and qualified platforms. As a Senior Manager / Deputy Director, this role defines integration architectures, sets technical direction, and drives cross-functional execution across device engineering, process development, packaging, and design enablement teams to deliver high-performance, scalable quantum hardware.

Essential Responsibilities

• Lead integration strategy for topological qubit platforms across materials, devices, interconnect, and system integration
• Define integration architectures combining topological, superconducting, and semiconductor technologies into scalable systems
• Drive development and integration of advanced materials, including III‑V heterostructures, epitaxy, and superconducting films
• Establish integration schemes for superconducting interconnects and BEOL wiring for low-loss cryogenic operation
• Lead integration of qubit devices and associated cryogenic control/read-out ICs
• Ensure alignment between device physics (coherence, noise, thermal behavior) and process capabilities
• Drive yield learning, variability reduction, and defectivity improvement using DOEs
• Define system-level tradeoffs across performance, yield, scalability, and cost
• Establish technical milestones, integration checkpoints, and key performance metrics
• Support hardware qualification, reliability, and manufacturability readiness
• Serve as primary technical interface to internal leadership, external partners, and research collaborators
• Communicate progress, risks, and mitigation strategies to executive stakeholders
• Build and lead a high-performance team, fostering technical rigor and innovation

Required Qualifications

• MS or PhD in Electrical Engineering, Physics, Materials Science, Applied Physics, or related field
• 12+ years of experience in semiconductor device, materials, or integration
• Strong knowledge of quantum-relevant materials (III‑V semiconductors, superconductors, topological materials)
• Experience with device physics and operation at cryogenic temperatures
• Proven experience leading cross-functional engineering programs
• Strong analytical, problem-solving, and communication skills

Preferred Qualifications

• PhD with experience transitioning research into manufacturable semiconductor technologies
• Experience with epitaxial growth (MBE, MOCVD) and heterostructure engineering
• Background in semiconductor-superconductor or topological/Majorana qubit systems
• Experience with BEOL integration, superconducting wiring, or low-loss interconnect
• Experience with 3D heterogeneous integration and advanced packaging
• Familiarity with cryogenic control/read-out IC architectures
• Experience collaborating with academic, government, or industry research programs

Expected Salary Range

The exact Salary will be determined based on qualifications, experience and location.