Quantum IC Package Substrate Design Engineer

Posted 2 Days Ago
Be an Early Applicant
Hillsboro, OR, USA
In-Office
122K-173K Annually
Senior level
Artificial Intelligence • Cloud • Information Technology • Software
Creating world-changing technology that enriches the lives of every person on earth.
The Role
Design large-form-factor IC substrates for Intel’s quantum computing systems using Siemens Xpedition. Responsibilities include high-speed routing, design validation with DRC and LVS, advanced 2.5D and 3D packaging integration, collaboration on signal, power, and thermal requirements, supplier tapeout, milestone communication, and technical documentation. The role requires substantial IC substrate design experience and supports innovative silicon quantum dot processor development.
Summary Generated by Built In
Job Details:

Job Description: 

Intel Corporation is the world's largest semiconductor company and a global leader in computing innovation. Our Quantum Computing Group represents Intel's bold venture into the next frontier of computing technology, leveraging our decades of semiconductor manufacturing expertise to develop silicon-based quantum processors. We're pioneering spin qubit technology in silicon quantum dots, combining cutting-edge quantum physics with Intel's unmatched manufacturing capabilities to create the world's first commercially viable quantum computers. Our collaborative approach spans Intel's research divisions and partnerships with leading academic institutions worldwide.
We are seeking an exceptional Quantum IC Substrate Package Layout Design Engineer to join our pioneering quantum computing team in Oregon. In this role you will be responsible for design of large form factor IC substrates within a multidisciplinary team. You'll play a crucial role in advancing Intel's silicon quantum dot technology while contributing to the development of scalable quantum systems that will revolutionize computing.
Key Responsibilities
- Design of IC substrates using Siemens Xpedition IC package design software
- Work closely with stakeholders to meet design requirements - e.g., receive feedback from silicon testchip, signal integrity (SI), power integrity (PI), thermal simulation, and system integration engineers
- Deliver and disseminate design milestones to stakeholders
- Design validation and verification; including DRC and LVS
- Advanced packaging design integration (2.5D and 3D) with IC substrate
- Tapeout of designs with substrate suppliers in collaboration with Intel substrate teams
- Communicate designs in presentations and relevant documentation
- Stay current with the latest developments in packaging technology and design techniques by attending conferences and reading papers
As a successful candidate, you must possess
- Excellent communication and presentation skills for technical and non-technical audiences
- Strong analytical thinking and problem-solving capabilities
- Collaborative mindset with ability to work effectively across diverse teams
- Adaptability to work in a fast-paced, innovative research environment
- Passion for pushing the boundaries of quantum technology development
Join Intel's Quantum Computing Group where we are building the future of quantum computing. If you're passionate about working at the forefront of quantum computing packaging and want to work with the resources and expertise of the world's leading semiconductor company, we want to hear from you. Apply today and discover your place in our world-changing work.

Qualifications:

You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Requirements listed would be obtained through a combination of relevant industry job experience, internship experience and/or schoolwork/classes/research.
Minimum Qualifications:
B.S. degree in Electrical Engineering, Computer Engineering, or a related field AND 5+ years of experience in IC substrate design for CPU, GPU, SoC/ASIC, and/or relevant design architectures.
OR M.S. degree in Electrical Engineering, Computer Engineering, or a related field AND 3+ years of experience in IC substrate design for CPU, GPU, SoC/ASIC, and/or relevant design architectures.


The experience must include:
- Siemens Xpedition design environment and workflow.
- High-speed signal routing.
- Experience with large form factor IC substrates.
Preferred Qualifications:
- 1+ years of experience with advanced routing engines for IC substrate design. Examples include AI and physics/model-based routing engines.

- Proficiency with understanding SI/PI/thermal impact on IC substrate design choices.

          

Job Type:Experienced Hire

Shift:Shift 1 (United States of America)

Primary Location: US, Oregon, Hillsboro

Additional Locations:

Posting Statement:All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.Position of TrustN/ABenefits

We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel.



Annual Salary Range for jobs which could be performed in the US: $122,440.00-172,860.00 USD

The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.

Work Model for this Role

This role will require an on-site presence. * Job posting details (such as work model, location or time type) are subject to change.

*

ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.

Skills Required

  • Bachelor’s degree in Electrical Engineering, Computer Engineering, or a related field and 5+ years of IC substrate design experience; or a master’s degree in a related field and 3+ years of experience
  • Experience designing IC substrates for CPU, GPU, SoC, ASIC, or relevant architectures
  • Experience with Siemens Xpedition design environment and workflow
  • Experience with high-speed signal routing
  • Experience with large-form-factor IC substrates
  • Experience with advanced routing engines for IC substrate design, including AI- or physics/model-based routing engines
  • Understanding of signal integrity, power integrity, and thermal impacts on IC substrate design choices
  • Excellent communication and presentation skills
  • Strong analytical thinking and problem-solving capabilities
  • Ability to collaborate effectively across diverse teams

Intel Compensation & Benefits Highlights

The following summarizes recurring compensation and benefits themes identified from responses generated by popular LLMs to common candidate questions about Intel and has not been reviewed or approved by Intel.

  • Leave & Time Off Breadth — Sabbaticals and paid time off are highlighted as signature elements, with an established program offering four weeks after four years or eight weeks after seven years. This distinctive time off is positioned as a meaningful part of the overall package.
  • Parental & Family Support — Paid bonding leave of 12 weeks and a New Parent Reintegration program, plus fertility benefits around $40,000 and up to $15,000 adoption reimbursement with no lifetime cap, are clearly stated. These programs are presented as standout components alongside broader family support resources.
  • Healthcare Strength — Multiple medical plan options with 2026 updates, a shift to Spring Health for EAP, and in‑network virtual medical visits covered at 100% beginning in 2026 indicate a comprehensive offering. These features signal an emphasis on robust medical access and mental health support.

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The Company
HQ: Santa Clara, CA
75,000 Employees
Year Founded: 1968

What We Do

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