The Board-Level Quality and Reliability Engineer is responsible for ensuring the quality, robustness, and long-term reliability of advanced semiconductor products throughout development, qualification, and production. The successful candidate will provide technical leadership in board-level reliability assessment, failure analysis, qualification methodology development, risk management, and industry standards engagement.
This role serves as the technical authority for board-level reliability of advanced packages, including BGA, LGA, and heterogeneous integration technologies. The engineer will lead reliability strategy development, qualification planning, and failure mechanism assessments while partnering closely with product development, packaging, manufacturing, suppliers, and customers.
The position also requires active participation and technical leadership within JEDEC and other industry standards organizations to influence future reliability requirements, qualification methodologies, and semiconductor packaging standards. JEDEC quality and reliability committees (JC-14) are identified as key industry forums for qualification methodologies, reliability testing, and standards development.
Key Responsibilities
Board-Level Reliability Engineer:
• Develop qualification plans covering thermal cycling, mechanical shock, vibration, drop, power cycling, humidity, and use-condition testing.
• Establish reliability requirements and acceptance criteria based on customer, market, and business needs.
• Lead risk assessments using FMEA, fault tree analysis, and reliability growth methodologies.
• Develop reliability demonstration plans and statistical confidence strategies.
Failure Analysis and Root Cause Investigation
• Lead complex reliability investigations and root-cause analyses.
• Drive corrective and preventive actions across product design, materials, assembly, and manufacturing processes.
Data Analytics / Reliability Statistics
• Perform Weibull analysis, DOE studies, and reliability statistics.
Standards Development and Industry Engagement
• Represent the company within JEDEC, IPC, AEC, and related standards organizations.
• Actively contribute to JEDEC JC-14 Quality and Reliability committees and subcommittees.
• Author, review, and ballot industry standards, technical publications, and qualification methodologies.
Behavioral traits:
Collaboration and Communication
Demonstrated ability to work within cross-functional teams consisting of design, process, manufacturing, quality, and supplier engineering organizations.
Ability to communicate technical findings and reliability risks to stakeholders in a clear and concise manner.
Strong technical writing skills for qualification reports, failure analysis summaries, and reliability assessments.
Minimum Qualifications
Education
Master's degree in Materials Science, Mechanical Engineering, Electrical Engineering, Reliability Engineering, Physics, or related technical field with 3+ years of industry experience, OR
Ph.D. in Materials Science, Mechanical Engineering, Electrical Engineering, Reliability Engineering, Physics, or related technical field with 1+ years of industry experience.
Technical Experience to be considered:
Experience in semiconductor package, board-level, or electronic system reliability.
Knowledge of reliability qualification methodologies including thermal cycling, mechanical shock, vibration, temperature-humidity testing, and accelerated stress testing.
Understanding of solder interconnect reliability, PCB technologies, SMT assembly processes, and package-to-board interactions.
Experience supporting failure analysis investigations and root cause determination.
Familiarity with reliability statistics, Weibull analysis, Design of Experiments (DOE), and data analysis techniques.
Working knowledge of FMEA, risk assessment methodologies, and reliability qualification planning.
Industry Standards
Familiarity with JEDEC reliability and qualification standards.
Interest in participating in industry standards organizations and technical working groups.
Ability to represent company positions in technical discussions with customers, suppliers, and industry partners.
Preferred Qualifications
Technical Expertise
Experience with advanced semiconductor packaging technologies including FCBGA, flip-chip, heterogeneous integration, chiplet-based architectures, or 2.5D/3D packaging.
Experience conducting board-level reliability testing and data interpretation.
Knowledge of thermo-mechanical failure mechanisms including solder fatigue, pad cratering, substrate cracking, delamination, and warpage effects.
Familiarity with finite element modeling (FEM) or physics-of-failure approaches.
Industry Engagement
Prior participation in JEDEC, IPC, or similar industry standards activities.
Experience reviewing or contributing to reliability specifications, qualification requirements, or industry guidance documents.
Attendance at industry conferences, technical symposiums, or standards committee meetings.
Professional Skills
Demonstrated initiative in driving reliability improvements and problem-solving efforts.
Ability to manage multiple projects and priorities in a fast-paced development environment.
Track record of successfully influencing technical decisions through data-driven analysis.
Job Type:Experienced HireShift:Shift 1 (United States of America)Primary Location: US, Arizona, PhoenixAdditional Locations:Posting Statement:All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.Position of TrustN/ABenefits
We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel.
Annual Salary Range for jobs which could be performed in the US: $120,860.00-170,630.00 USD
The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.
Work Model for this Role
This role will require an on-site presence. * Job posting details (such as work model, location or time type) are subject to change.*
ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.Skills Required
- Master's degree in Materials Science, Mechanical Engineering, Electrical Engineering, Reliability Engineering, Physics, or related technical field with 3+ years industry experience OR Ph.D. in relevant field with 1+ years industry experience.
- Experience in semiconductor package, board-level, or electronic system reliability.
- Knowledge of reliability qualification methodologies including thermal cycling, mechanical shock, vibration, temperature-humidity testing, and accelerated stress testing.
- Understanding of solder interconnect reliability, PCB technologies, and SMT assembly processes.
- Experience supporting failure analysis investigations and root cause determination.
- Familiarity with reliability statistics, Weibull analysis, Design of Experiments (DOE), and data analysis techniques.
- Working knowledge of FMEA, fault tree analysis, and reliability qualification planning.
- Familiarity with JEDEC reliability and qualification standards and ability to represent company in technical discussions.
- Experience with advanced semiconductor packaging technologies including FCBGA, flip-chip, heterogeneous integration, chiplet-based architectures, or 2.5D/3D packaging.
- Experience conducting board-level reliability testing and data interpretation.
- Knowledge of thermo-mechanical failure mechanisms (solder fatigue, pad cratering, substrate cracking, delamination, warpage).
- Familiarity with finite element modeling (FEM) or physics-of-failure approaches.
- Prior participation or contribution to JEDEC, IPC, or similar industry standards activities.
- Strong technical writing, cross-functional collaboration, and ability to manage multiple projects and influence decisions through data-driven analysis.
Intel Compensation & Benefits Highlights
The following summarizes recurring compensation and benefits themes identified from responses generated by popular LLMs to common candidate questions about Intel and has not been reviewed or approved by Intel.
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Leave & Time Off Breadth — Sabbaticals and paid time off are highlighted as signature elements, with an established program offering four weeks after four years or eight weeks after seven years. This distinctive time off is positioned as a meaningful part of the overall package.
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Parental & Family Support — Paid bonding leave of 12 weeks and a New Parent Reintegration program, plus fertility benefits around $40,000 and up to $15,000 adoption reimbursement with no lifetime cap, are clearly stated. These programs are presented as standout components alongside broader family support resources.
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Healthcare Strength — Multiple medical plan options with 2026 updates, a shift to Spring Health for EAP, and in‑network virtual medical visits covered at 100% beginning in 2026 indicate a comprehensive offering. These features signal an emphasis on robust medical access and mental health support.
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