Product Failure Analysis Engineer - SCAN Design for Test

Job Details:

Job Description: 

At Intel, we create world-changing technology that enriches the lives of every person on earth. As a global leader in semiconductor innovation, we design and manufacture the world's most advanced chips — powering everything from personal computers and smartphones to data centers, AI systems, and autonomous vehicles. Our Oregon campus is one of our most important engineering hubs in the world, home to thousands of brilliant engineers who are shaping the future of technology. We believe that diversity of thought, background, and experience makes us stronger — and we're committed to building a workplace where everyone can do their best work.

We are seeking an experienced Product Failure Analysis Engineer - SCAN Design for Test who is excited by the opportunity to help enable the success of Intel Foundry's leading-edge 18A technology. The ideal candidate brings 6-12 years of semiconductor experience with deep expertise in DFT, ATPG, scan diagnosis, and post-silicon debug, along with a proven track record of solving complex silicon issues in advanced process technologies.

In this role, you will play a critical part in accelerating the ramp and quality of Intel Foundry products by driving root-cause analysis of silicon failures, partnering across design, test, technology development, and manufacturing organizations to quickly identify and resolve product and process issues. Your technical leadership will directly contribute to improving product quality, yield, reliability, and time-to-market for next-generation foundry customers.

The successful candidate will have hands-on experience utilizing both logical diagnosis techniques (ATPG, scan diagnosis, fault isolation) and physical failure analysis methodologies (FIB, SEM, TEM, laser-based techniques, or equivalent) to isolate defects and determine corrective actions. Strong collaboration skills are essential, as you will work closely with DFT architects, design engineers, validation teams, process integration engineers, yield engineers, and high-volume manufacturing organizations.

Beyond issue resolution, we are looking for an engineer who can help shape the future of failure analysis and silicon debug by developing innovative methodologies, automation frameworks, and diagnostic capabilities that improve debug efficiency and accelerate root-cause identification across Intel Foundry's advanced technology portfolio..

Key Responsibilities:

• Lead Failure Analysis: Utilize state-of-the-art lab equipment — including FIB tools, probe tools, and automated systems — to isolate microscopic silicon circuit failures and identify root causes with precision and speed.
• Drive Cross-Functional Collaboration: Partner with test and validation engineers, circuit designers, wafer fabrication process engineers, and high-volume manufacturing teams to resolve quality issues, develop temporary mitigations, and implement permanent remedies.
• Advance Debug Technologies: Develop new debug tools, methodologies, and technologies that push the boundaries of silicon debug, contributing to breakthrough innovations in semiconductor manufacturing.
• Ensure Design for Debug: Evaluate and resolve component engineering and physical design issues, ensuring products incorporate the necessary design-for-debug features to enable deep silicon isolation capabilities.
• Support Continuous Improvement: Provide expert input on failure analysis investigation areas and design process improvements, ensuring products consistently perform to specification.

 

As a Successful Candidate, You Will Bring:

• A collaborative spirit — you thrive in cross-functional environments and build strong relationships across teams.
• Intellectual curiosity — you love diving deep into complex problems and aren't satisfied until you've found the root cause.
• Resilience and adaptability — you stay focused and effective even when working on the most challenging, ambiguous problems.
• Clear communication — you can translate highly technical findings into clear, actionable insights for diverse audiences.
• Ownership mentality — you take pride in your work and hold yourself accountable for delivering results.
• Innovation mindset — you're always looking for better ways to do things and aren't afraid to challenge the status quo.

Ideal Background:

• 6+ years of semiconductor industry experience in Product Engineering, Failure Analysis, Silicon Debug, DFT, Yield Engineering, or Post-Silicon Validation.
• Deep expertise in DFT architectures, ATPG, scan diagnosis, and fault modeling.
• Experience debugging complex silicon issues on leading-edge technology nodes.
• Strong understanding of failure analysis workflows and physical debug techniques.
• Demonstrated success driving cross-functional investigations from problem identification through corrective action.
• Experience developing automation and debug methodologies that improve diagnosis accuracy and turnaround time.
• Passion for advancing semiconductor technology and contributing to the successful deployment of Intel Foundry 18A products.

If you're passionate about silicon engineering and want to work on technology that matters, we'd love to hear from you. Apply today and take the next step in your career at Intel.

 

Qualifications:

You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Experience would be obtained through a combination of prior education level classes, and current level school classes, projects, research and relevant previous job and/or internship experience.

Minimum Qualifications:

• Bachelor’s degree in electrical engineering, computer engineering, or a related STEM discipline with 6+ years of hands-on experience, OR master's degree with 4+ years, OR PhD with 2+ years.
• Hands – on experience with the following:
  • Expertise in Design for Test (DFT) tools and techniques, SCAN ATPG methodology, and Scan Chain Diagnosis.
  • In fault isolation techniques including ATPG pattern generation, fault modeling (stuck-at, transition, path delay, bridging), and Scan architecture (SSN).
  • Experience with Siemens Tessent, Synopsys TestMAX/TetraMAX, Verdi, DVE, simulation and diagnosis tools
  • Experience developing debug automation and analysis tools using Python, Perl, or TCL

Preferred Qualifications:

• 6+ years of experience:
  • JTAG and validation/debug research methodologies.
  • Developing innovative debug tools and methodologies in a research-driven environment.
  • In foundry, fabless semiconductor, or high-volume manufacturing environments supporting customer product bring-up, yield ramp, or production qualification.

          

Job Type:Experienced Hire

Shift:Shift 1 (United States of America)

Primary Location: US, Oregon, Hillsboro

Additional Locations:

Posting Statement:All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.Position of TrustN/ABenefits

We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel.

Annual Salary Range for jobs which could be performed in the US: $141,910.00-269,100.00 USD

The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.

Work Model for this Role

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.

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ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.