Process Integration Engineer

Posted 7 Days Ago
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Alhambra, CA, USA
In-Office
93K-135K Annually
Senior level
Internet of Things • Semiconductor
The Role
Lead end-to-end integration of InP wafer fabrication flows for DFB lasers, SOAs, and gain chips. Own process compatibility across lithography, etch, deposition, metallization; drive yield analysis, excursion response, failure analysis, root-cause resolution, NPI support, documentation, and process control to enable robust, high-yield manufacturing.
Summary Generated by Built In

Location: Alhambra, CA (Onsite)

Position Summary: The Process Integration Engineer – InP Wafer Fab position is responsible for end-to-end ownership of Indium Phosphide (InP) wafer fabrication process flows supporting the manufacturing of DFB lasers, Semiconductor Optical Amplifiers (SOAs), and Gain Chip (GC) products. This role serves as the technical integrator across all wafer fab process modules, ensuring compatibility, robustness, and high-yield performance of the complete device fabrication flow The position focuses on cross-module coordination, yield analysis, failure analysis, and root-cause resolution to enable stable manufacturing operations and successful new product introduction. The role requires strong systems-level understanding of InP device fabrication, data-driven problem solving, and close collaboration with process, device, reliability, and manufacturing teams. 

 

Responsibilities:  

End-to-End Process Flow Ownership and Integration (35%): 

  • Own and manage the complete InP wafer fabrication process flow from epitaxy through backend processing 

  • Ensure process compatibility and robust integration across lithography, etch, deposition, metallization, and test modules 

  • Define and maintain integration requirements including layer interactions, thermal budgets, process margins, and sequence dependencies 

  • Serve as the primary technical owner for process flow integrity and change impact assessment 

Yield Analysis, Excursion Response, and Continuous Improvement (25%): 

  • Lead yield analysis efforts to identify yield limiters, systematic defects, and process interactions 

  • Drive excursion response activities, including rapid containment, root-cause identification, and corrective action implementation 

  • Analyze inline and electrical test data to identify process trends and emerging risks 

  • Partner with manufacturing and process teams to implement yield improvement and defect reduction initiatives 

Failure Analysis and Root-Cause Resolution (20%): 

  • Lead and coordinate failure analysis (FA) activities using structured problem-solving methodologies (e.g., 8D, Six Sigma) 

  • Identify defect mechanisms and process-induced failure modes through cross-functional investigation 

  • Leverage FA techniques such as optical inspection, SEM, FIB, SIMS, and electrical analysis (directly or via partners) 

  • Ensure corrective and preventive actions are implemented and verified for effectiveness 

New Product Introduction and Technology Support (10%): 

  • Support new product introduction (NPI), process transfers, and technology changes within the InP wafer fab 

  • Evaluate integration risks associated with new designs, materials, or process changes 

  • Collaborate with device and design teams to ensure manufacturability and integration robustness 

Documentation, Process Control, and Manufacturing Support (10%): 

  • Author and maintain process flows, integration specifications, travelers, and control plans 

  • Define requirements for process control monitor structures (PCM/TLM) and ensure implementation in design layouts 

  • Support day-to-day manufacturing operations by providing technical guidance and integration expertise 

  • Ensure documentation accuracy and compliance with internal quality and manufacturing standards 

 

Minimum Qualifications: 

  • Bachelor’s degree or higher in Electrical Engineering, Materials Science, Physics, Chemical Engineering, or a related field required 

  • Minimum of 5+ years of experience in semiconductor process integration or device fabrication 

  • Strong hands-on understanding of InP-based or III-V compound semiconductor wafer fabrication processes 

  • Demonstrated experience with yield analysis, defect reduction, and root-cause methodologies 

  • Experience working across multiple wafer fab process modules in a manufacturing environment 

  • Strong systems-level understanding of semiconductor device fabrication and process interactions 

  • Proficiency in data analysis and statistical process control (SPC) 

  • Ability to drive alignment and decision-making across cross-functional engineering teams 

  • Preferred experience with DFB lasers, SOAs, gain chips, or photonic device manufacturing 

  • Familiarity with reliability testing, qualification flows, and product lifecycle support preferred 

  • Experience supporting high-mix, low-volume manufacturing environments preferred 

 

The intent of this job description is to describe the major duties and responsibilities performed by incumbents of this job. Incumbents may be required to perform job-related tasks other than those specifically included in this description. 

 

All duties and responsibilities are essential job functions and requirements and are subject to possible modification to reasonably accommodate individuals with disabilities. 

 

A reasonable estimate of the pay range for this position is $93,000 - $135,000.  There are several factors taken into consideration in determining base salary, including but not limited to: job-related qualifications, skills, education and experience, as well as job location and the value of other elements of an employee’s total compensation package. 

#LI-Onsite

Skills Required

  • Bachelor's degree or higher in Electrical Engineering, Materials Science, Physics, Chemical Engineering, or related field
  • Minimum of 5+ years of experience in semiconductor process integration or device fabrication
  • Hands-on understanding of InP-based or III-V compound semiconductor wafer fabrication processes
  • Experience working across multiple wafer fab process modules in a manufacturing environment (epitaxy, lithography, etch, deposition, metallization, test)
  • Demonstrated experience with yield analysis, defect reduction, and root-cause methodologies
  • Proficiency in data analysis and statistical process control (SPC)
  • Strong systems-level understanding of semiconductor device fabrication and process interactions
  • Ability to drive alignment and decision-making across cross-functional engineering teams
  • Familiarity with failure analysis techniques and tools (optical inspection, SEM, FIB, SIMS, electrical analysis)
  • Preferred experience with DFB lasers, SOAs, gain chips, or photonic device manufacturing
  • Familiarity with reliability testing, qualification flows, and product lifecycle support
  • Experience supporting high-mix, low-volume manufacturing environments

Semtech Compensation & Benefits Highlights

The following summarizes recurring compensation and benefits themes identified from responses generated by popular LLMs to common candidate questions about Semtech and has not been reviewed or approved by Semtech.

  • Parental & Family Support Up to 20 weeks of paid maternity/parental leave is highlighted in multiple regions. Enhanced leave is positioned as a core part of the package.
  • Healthcare Strength Medical, dental, and vision coverage are standard elements of the offering. Core health coverage features prominently alongside other benefits.
  • Leave & Time Off Breadth Paid vacation and time‑off programs are explicitly included. Time off is emphasized together with flexible/hybrid work policies where possible.

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The Company
HQ: Camarillo, CA
1,475 Employees
Year Founded: 1960

What We Do

Semtech Corporation is a high-performance semiconductor, IoT systems and Cloud connectivity service provider dedicated to delivering high quality technology solutions that enable a smarter, more connected and sustainable planet.

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