Principal Solutions Engineer- AE

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

·        Develop and implement comprehensive PDN analysis methodologies for complex 3DIC packages, including CPU, GPU, and TPU structures. 

·        Perform detailed power noise and signal integrity simulations using tools like Cadence Sigrity PowerSI, Ansys HFSS, or equivalent. 

·        Identify and resolve power integrity issues, such as IR drop, ground bounce, and signal noise, to achieve sign-off criteria. 

·        Analyze and optimize signal integrity for high-speed interfaces in 3DIC packages, including HBM3, UCIE, and DDR5. 

·        Perform advanced SI simulations using industry-standard tools like Cadence Clarity, HyperLynx, Ansys HFSS, or equivalent. 

·        Extract parasitic from 3D package layout and integrate them into SI simulations. 

·        Develop and implement design rules and guidelines for 3DIC package signal integrity. 

·        Collaborate with design engineers, layout engineers, and thermal engineers to optimize the PDN design and ensure proper heat dissipation. 

·        Stay up-to-date on emerging 3DIC technologies and trends and propose innovative solutions to improve power integrity performance. 

·        Document analysis results and findings clearly and concisely for internal and external stakeholders. 

·        Participate in technical discussions and provide expert guidance on signal/power integrity matters. 

·        Master’s degree in electrical engineering, Computer Engineering, or a related field (PhD preferred) 

·        10+ years of experience in SIPI or related field, In-depth knowledge of PDN design principles, including modeling, simulation, and optimization techniques. 

·        Expertise in advanced SI simulation tools like Cadence Sigrity, Clarity, HyperLynx, HFSS, or equivalent. 

·        Proven experience in leading and managing complex engineering projects 

·        In-depth knowledge of 3D-IC packaging technologies, including chip stacking, interposers, and through-silicon vias (TSVs) 

·        Proven experience with high-speed interface design and analysis (HBM, DDR, PCIe, etc.). 

·        Strong understanding of thermal, signal integrity, and power integrity concepts 

·        Excellent written and verbal communication skills. 

·        Ability to work effectively in a team environment. 

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