Principal Software Engineer (Verification of VIP using Verilog/SV/UVM )

Job Description:

Job Title:  ( Verification of VIP using Verilog/SV/UVM – Ahmedabad )

Cadence is a pivotal leader in electronic design, building upon more than 30 years of computational software expertise. The company applies its underlying Intelligent System Design strategy to deliver software, hardware and IP that turn design concepts into reality.  Cadence customers are the world’s most innovative companies, delivering extraordinary electronic products from chips to boards to systems for the most dynamic market applications including consumer, hyperscale computing, 5G communications, automotive, aerospace industrial and health.

The Cadence Advantage

• The opportunity to work on cutting-edge technology in an environment that encourages you to be creative, innovative, and to make an impact.
• Cadence’s employee-friendly policies focus on the physical and mental well-being of employees, career development, providing opportunities for learning, and celebrating success in recognition of specific needs of the employees.
• The unique “One Cadence – One Team” culture promotes collaboration within and across teams to ensure customer success.
• Multiple avenues of learning and development available for employees to explore as per their specific requirement and interests.
• You get to work with a diverse team of passionate, dedicated, and talented individuals who go above and beyond for our customers, our communities, and each other—every day.

Job Summary:

We are looking for a candidate with excellent communication skills and ability to ramp up on new technologies quickly and independently. This position requires the technical expertise in protocol and formal verification methodologies.

This an excellent opportunity to work in a supportive and friendly work environment, where we are vested in each other’s success, and are passionate about technology and innovation.

Job responsibilities: 

Work location :  Ahmedabad

Work Experience : 8+ Years OR equivalent relevant years of experience.

Verification of VIP using Verilog/SV/UVM – (Ahmedabad)

CV to send K Madhu Prasad [email protected]

Job responsibilities: 

• Responsible for verification of VIP using Verilog/SystemVerilog/UVM
• Involve in managing multiple VIPs, leading a small team, and interacting with customers. 

Requirements:

• B.Tech./M.Tech. degree in Electronic and Communication or a related technical field with relevant 8+ years of experience.
• Knowledge of Verilog/System Verilog languages and UVM verification methodologies.
• Experience and Knowledge of the EDA tool flow for Front end verification like creating test plan based on specification, write and simulate test cases, identify bugs, validate fixes etc.
• Generate the functional coverage report, identify the test scenarios to fill the coverage wholes, write more tests to improve the coverage.
• Strong analytical and problem-solving skills with an ability to visualize processes and outcomes.
• Outstanding all-round communication skills and ability to work collaboratively in a dynamic multi-location environment.

Strong Plus:

• Protocol understanding for various DRAM memory interface like DDR4/5, LPDDR4/5, HBM3/4, GDDR6/7 or any other storage protocol.
• Experience with digital logic design or IP/SoC level Verification flow.

Regards

Madhu/-

K Madhu Prasad