Principal Silicon Technologist

Job Description:

Astera Labs is looking for a silicon technologist with experience working with foundries driving down defect density, analyzing critical silicon parameters and providing ownership of all interactions between Astera Labs and the foundry. The candidate must have a proven track record of working across the fab to monitor and provide input to increase yields as well as design-technology co-optimization. Responsibilities included but not limited to:

• Lead technical discussions with the foundry during all aspects of product development from concept to HVM.
• Responsible for product tapeout technical communication between Astera Labs and the foundry.
• Interface with foundry on PDK library, DFM rules, defect density, yield prediction, failure analysis, yield improvement, and process correlation for all Astera Labs products.
• Responsible for process fine tuning to optimize the power, performance and yield
• Define process split for PVT characterization per process node.
• Dive deep into process parameters to understand their impact on product yields and performance.
• Work with IP vendor, design, and foundry to review and sign off DFM violations.
• Ownership of foundry technology roadmaps outlining schedule, cost, performance parameters, node selection, and technology intercept.
• Aligning specific IP feature requirements and the foundry capability.
• Setup and maintain quarterly reviews with the foundry.

Basic Qualifications:

• Minimum of 10 years of experience in the field of technology development working with complex SOC, including high-speed XCVR.
• Strong academic/technical background in Electrical Engineering, Material Science or equivalent; MS is required; PhD preferred.
• Proven track record is the lead individual with foundries supporting different deep sub-micron process nodes.
• Strong statistical and data analysis skills, teamwork, and communication skills. 

Required experience:

• Experience working between the foundry and the physical design team to assess design rule requirements to meet product specs (electrical, physical, and package).
• Experience holding foundries accountable for process performance and meeting agreed product yield objectives.
• Experience in foundry integration and device modeling.
• Technical lead role in having gone through at least one product development life cycle from concept to production.

Preferred experience:

• Experience in multi-die development, including optics.
• Experience in qualification tests to support NPI productization, bump houses, and foundry process changes.
• Experience in high-speed design techniques.
• Experience in product cost models based on the die size, product features, and foundry input. 

The base salary range is $160,000.00 USD – $240,000.00 USD. Your base salary will be determined based on your location, experience, and the pay of employees in similar positions.