Principal RTL Design Engineer, IO & Memory Systems

Posted 2 Days Ago
Be an Early Applicant
2 Locations
In-Office
180K-255K Annually
Senior level
Artificial Intelligence • Hardware • Machine Learning • Natural Language Processing • Software • Generative AI
SambaNova is the #1 platform for business AI.
The Role
Owns architecture, microarchitecture, RTL design, integration, and implementation of high-speed I/O and memory subsystems for AI accelerator platforms. Responsibilities include SystemVerilog development, front-end design flows, protocol and vendor IP integration, PPA optimization, timing closure, verification collaboration, issue resolution, and cross-functional lifecycle execution from architecture through silicon.
Summary Generated by Built In

SambaNova is a leader in next-generation AI infrastructure, delivering a full-stack inference platform for customers worldwide. At the core of SambaNova's technology is the RDU (Reconfigurable Dataflow Unit) — a chip built on a dataflow architecture rather than the traditional GPU model. Its decode performance is especially strong for agentic workloads like multi-turn agents, code generation, and long-running applications. RDUs are packaged into SambaRack, rack-scale hardware that lets customers deploy state-of-the-art models with better performance, greater energy efficiency, and faster time to value.

About the role

SambaNova is seeking a Principal Engineer to own the design, integration, and implementation of high-speed IO and memory subsystems within the DataScale® platform. This role is central to delivering reliable, high-performance AI systems at scale.

You will drive these subsystems across the full product lifecycle, from architecture exploration and microarchitecture definition through RTL and integration of internal and third-party IP (PCIe, Ethernet , CXL, HBM, die-to-die). This is a hands-on role for an engineer with deep protocol and RTL expertise, who can operate in ambiguity and execute with high ownership.

Responsibilities
  • Engage in architecture exploration with system and chip architects to define IO and memory subsystem direction
  • Drive feasibility studies and design trade-off analysis to meet PPA constraints
  • Own microarchitecture definition and specification for IO and memory subsystems
  • Deliver synthesizable, high-quality SystemVerilog RTL for assigned blocks against functionality, performance, and power targets
  • Run the front-end design flow end to end, covering lint, CDC/RDC, synthesis, timing constraint development, and design-for-test readiness
  • Partner with STA and physical design teams on timing closure, floorplanning, congestion analysis, and optimization at advanced process nodes
  • Work closely with verification and emulation teams to ensure design validation coverage and quality
  • Collaborate with software and firmware teams to ensure optimal end-to-end solutions
  • Drive cross-functional triage of complex functional and performance issues to root cause and closure
  • Apply engineering best practices including code review, testing, and refactoring
  • Improve design and integration methodology, reuse, and flow scalability
Required Qualifications
  • MS in Electrical Engineering, Computer Science, or a related field
  • 7+ years of experience in ASIC design
  • Experience in logic design, microarchitecture, specification, SystemVerilog RTL design, and functional verification
  • Experience with power, performance, or area optimization
  • Experience with two or more on-chip or chip-to-chip protocols and interfaces such as AXI, APB, PCIe, Ethernet, or UCIe
  • Experience with memory subsystems such as HBM and CXL
  • Ability to evaluate and select vendor IP, and to read and distill complex IP and protocol specifications into actionable design requirements
  • Clear and effective communicator with a proactive, collaborative approach to problem-solving
Preferred Qualifications
  • Experience taking one or more ASIC products from concept to silicon
  • Familiarity with emerging scale-up protocols (ESUN, SUE, UAL) and scale-out protocols such as Ultra Ethernet
  • Experience designing on-chip interconnect and traffic-management logic, including NoC fabrics, switches, arbiters, and quality-of-service or congestion control mechanisms
  • Knowledge of machine learning and hardware accelerator architectures

Base Salary Range:

Base Pay Range
$180,000$255,000 USD

Submission Guidelines
Please note that in order to be considered an applicant for any position at SambaNova Systems, you must submit an application form for each position for which you believe you are qualified. 

EEO Policy
SambaNova Systems is an Equal Opportunity/Affirmative Action Employer. All qualified applicants will receive consideration for employment without regard basis of age (40 and over), color, disability, gender identity, genetic information, marital status, military or veteran status, national origin/ancestry, race, religion, creed, sex (including pregnancy, childbirth, breastfeeding), sexual orientation, and any other applicable status protected by federal, state, or local laws.

Benefits Summary for US-Based, Full-Time Employment Positions
SambaNova offers a competitive total rewards package, including the base salary, plus equity and benefits. We cover 95% premium coverage for employee medical insurance, and 77% premium coverage for dependents and offer a Health Savings Account (HSA) with employer contribution. We also offer Dental, Vision, Short/Long term Disability, Basic Life, Voluntary Life, and AD&D insurance plans in addition to Flexible Spending Account (FSA) options like Health Care, Limited Purpose, and Dependent Care. Our library of well-being benefits available to you and your dependents includes a full subscription to Headspace, Gympass+ membership with access to physical gyms, One Medical membership, counseling services with an Employee Assistance Program, and much more.

Skills Required

  • Master’s degree in Electrical Engineering, Computer Science, or a related field
  • 7+ years of ASIC design experience
  • Experience in logic design, microarchitecture, specification, SystemVerilog RTL design, and functional verification
  • Experience with power, performance, or area optimization
  • Experience with at least two on-chip or chip-to-chip protocols or interfaces, such as AXI, APB, PCIe, Ethernet, or UCIe
  • Experience with memory subsystems such as HBM and CXL
  • Ability to evaluate and select vendor IP and interpret complex IP and protocol specifications
  • Clear communication and proactive, collaborative problem-solving skills
  • Experience taking one or more ASIC products from concept to silicon
  • Familiarity with emerging scale-up protocols such as ESUN, SUE, and UAL, and scale-out protocols such as Ultra Ethernet
  • Experience designing on-chip interconnect and traffic-management logic, including NoC fabrics, switches, arbiters, QoS, or congestion control
  • Knowledge of machine learning and hardware accelerator architectures
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The Company
HQ: Palo Alto, CA
500 Employees
Year Founded: 2017

What We Do

AI is changing the world and at SambaNova, we believe that you don’t need unlimited resources to take advantage of the most advanced, valuable AI capabilities - capabilities that are helping organizations explore the universe, find cures for cancer, and giving companies access to insights that provide a competitive edge. We deliver the world’s fastest and only complete AI solution for enterprises and governments with world-record inference performance and accuracy. Powered by the SambaNova SN40L Reconfigurable Dataflow Unit (RDU), organizations can build a technology backbone for the next decade of AI innovation with SambaNova Suite. Our fully integrated hardware-software system, DataScale®, enables organizations to train, fine-tune, and deploy the most demanding AI workloads using the largest and most challenging models. Most recently, with the launch of our newest offering, SambaNova Cloud, developers can supercharge AI-powered applications on Llama 3.2 models. SambaNova was founded in 2017 in Palo Alto, California, by a group of industry luminaries, business leaders, and world-class innovators who understand AI. Today, we’ve built an incredibly smart and motivated team dedicated to making a lasting impact on the industry and equipping our customers to thrive in the new era of AI.

Why Work With Us

As a talent first company, we aim to hire the greatest and most innovative minds in the industry- driving the next generation of AI computing where no barrier is too high and the possibilities are truly limitless. We encourage our peers to take risks and take the initiative to make a lasting impact on the AI and ML industries.

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