Principal Product Engineer, Synthesis

Seeking a highly motivated engineer who can drive improvement to Cadence’s synthesis and place & route products from a design perspective. The position provides an excellent opportunity to work closely with the R&D team to define the roadmap of the products.

Job responsibilities:

• Perform Product Engineering work for Genus Synthesis Solution (Genus), a logic synthesis software used for synthesizing a design described in a high-level language into logic gates, to achieve best-in-class Power, Performance & Area (PPA) for latest digital ASICs
• Understand the internal flow within the Genus for newly developed features and verify the correctness and perform experiments to determine an optimal solution
• Solve new and challenging problems in physical aware synthesis space with the goal to bridge the gap between logic synthesis and place and route
• Support the field engineers in Cadence Design Systems, Inc. and its customers in using Genus. In addition, interface between R&D and customer as the first line of support for the R&D and the customers
• Provide support to verify the interoperability of Genus with other digital logic software tools within Cadence Design Systems, Inc. to provide seamless flows
• Understand the future requirements of the software by interfacing with the internal and external customers of Genus and document the Product Requirement Specifications (PRS) for newly developed features using the standard documentation software

Preferred Qualifications:

• Requires a MS in Electrical Engineering or ECE with focus on VLSI with two or more years of relevant industrial experience
• Experience in design and EDA with an emphasis on Cadence tools of Synthesis, Physical Design & timing closure at 20nm or below nodes
• Prior Designer, Product Engineering or Application Engineering experience in digital implementation, especially synthesis
• Understand industry challenges in digital implementation & sign off domain with exposure to 28nm & below foundry process nodes
• Industry experience with EDA tools in the IC digital implementation flow, preferably on Genus and Innovus
• Experience in Logic Design and Synthesis, Formal Verification, Low Power design, Physical Design and Timing Closure for block level and top level designs
• Automation skills using Perl, Tcl and shell scripting essential
• Knowledge of HDL – Verilog or System Verilog is preferred
• Must have logic design and timing closure skills
• Strong analysis skills required to debug complex timing closure, logical and physical design problems. Ability to perform root-cause analysis to suggest solutions to customers and provide feedback to R&D
• Proven track record and experience working in a fast paced environment

The annual salary range for California is $136,500 to $253,500. You may also be eligible to receive incentive compensation: bonus, equity, and benefits. Sales positions generally offer a competitive On Target Earnings (OTE) incentive compensation structure. Please note that the salary range is a guideline and compensation may vary based on factors such as qualifications, skill level, competencies and work location. Our benefits programs include: paid vacation and paid holidays, 401(k) plan with employer match, employee stock purchase plan, a variety of medical, dental and vision plan options, and more.