This position involves:
- Interfacing with customers regarding digital reference flow requirements, including
- Synthesis
- Floorplanning
- Clock tree synthesis
- Power planning
- Place and route
- Timing closure
- Sign-off
- Capturing reference flow requirements, scoping effort on reference flow development
- Creating baseline flows to be used by customers as starting point for digital implementation
- Using baseline flow to implement test cases for process certification and validation
- Using implementation testcases for Tempus and Voltus sign-off
- Creating documentation explaining the theory and use behind reference flow steps and commands
- PPA optimization
Position requires:
- Bachelor’s degree with at least 12-15 years of design/EDA experience or Master’s degree with at least 10 years of experience. Master’s degree preferred.
- Strong knowledge in Digital Design Flows, Static Timing Analysis and EMIR is required
- Prior experience with ASIC digital implementation flows and EDA tools is required; Experience with advanced FinFet nodes (7nm and below) required. Experience with GAA technologies (2nm and below) preferred.
- Good programming knowledge in Unix, Shell scripting, perl and importantly TCL
- Strong customer-facing communication and problem-solving skills
- Strong personal drive for continuous learning and expanding professional skill sets
- Excellent verbal and written communication skills
Familiar with EDA tool operation, setup and debug:
- Digital: Genus, Innovus, Tempus, Voltus, etc
Skills Required
- Bachelor's degree with 12-15 years design/EDA experience
- Master's degree with at least 10 years experience (Master's preferred)
- Strong knowledge in Digital Design Flows
- Static Timing Analysis
- EMIR
- Experience with ASIC digital implementation flows and EDA tools
- Experience with advanced FinFET nodes (7nm and below)
- Experience with GAA technologies (2nm and below)
- Programming knowledge: Unix, Shell scripting, Perl, TCL
- Strong customer-facing communication and problem-solving skills
- Strong personal drive for continuous learning
- Excellent verbal and written communication skills
- Familiarity with EDA tool operation, setup and debug: Genus, Innovus, Tempus, Voltus
Cadence Design Systems Compensation & Benefits Highlights
The following summarizes recurring compensation and benefits themes identified from responses generated by popular LLMs to common candidate questions about Cadence Design Systems and has not been reviewed or approved by Cadence Design Systems.
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Equity Value & Accessibility — A discounted ESPP with a lookback feature and equity included in total compensation make ownership broadly accessible and potentially meaningful. Structured compensation at an industry leader adds predictability to equity participation.
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Healthcare Strength — Medical, dental, and vision coverage are described as solid, with mental‑health/EAP and fertility support enhancing the offering. The breadth across core care and family‑building needs strengthens the healthcare package.
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Leave & Time Off Breadth — Global Recharge Days, volunteer time off, and companywide breaks indicate a comprehensive time‑off framework. In addition, many salaried roles are described as having flexible or generous PTO policies.
Cadence Design Systems Insights
What We Do
Cadence enables electronic systems and semiconductor companies to create the innovative end products that are transforming the way people live, work and play. Cadence® software, hardware and IP are used by customers to deliver products to market faster. The company's Intelligent System Design strategy helps customers develop differentiated products—from chips to boards to intelligent systems—in mobile, consumer, cloud, data center, automotive, aerospace, IoT, industrial and other market segments. Cadence is listed as one of Fortune Magazine's 100 Best Companies to Work For.
