About SiFive
As the pioneers who introduced RISC-V to the world, SiFive is transforming the future of compute by bringing the limitless potential of RISC-V to the highest performance and most data-intensive applications in the world. SiFive’s unrivaled compute platforms are continuing to enable leading technology companies around the world to innovate, optimize and deliver the most advanced solutions of tomorrow across every market segment of chip design, including artificial intelligence, machine learning, automotive, data center, mobile, and consumer. With SiFive, the future of RISC-V has no limits.
At SiFive, we are always excited to connect with talented individuals, who are just as passionate about driving innovation and changing the world as we are.
Our constant innovation and ongoing success is down to our amazing teams of incredibly talented people, who collaborate and support each other to come up with truly groundbreaking ideas and solutions. Solutions that will have a huge impact on people's lives; making the world a better place, one processor at a time.
Are you ready?
To learn more about SiFive’s phenomenal success and to see why we have won the GSA’s prestigious Most Respected Private Company Award (for the fourth time!), check out our website and Glassdoor pages.
Job Description:
Responsibilities
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Lead implementation and drive uARCH optimization of SiFive’s high performance Out of Order RISC-V CPU's from RTL to GDSII
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Close ambitious performance, power, and area (PPA) goals at block and/or CPU subsystem level
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Collaborate closely with the microarchitecture and RTL teams to identify and optimize PPA trade offs, also includes path finding for next generation of CPUs
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Create timing and area models for configurability for predictable execution
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Contribute to physical implementation flow development and Foundation IP (standard cell, SRAM) improvement to drive best-in-class automation and PPA
Requirements
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12+ years of physical implementation experience with multiple tape outs in a wide range of technologies; Experience with CPU implementation and advanced process nodes (3nm and below) is strongly preferred;
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Well versed with Synopsys/Cadence Silicon Implementation tools
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Expertise in aggressive PPA optimization through physical design techniques
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Working knowledge for out of order core uArch and logic design is strongly preferred
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Prior experience in leading/managing teams is preferred
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Attention to detail and a focus on high-quality design
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Ability to work well with others and a belief that engineering is a team sport
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Bachelor’s or Master’s degree in Electrical Engineering or Computer Engineering
Additional Information:
This position requires a successful background and reference checks and satisfactory proof of your right to work in:
India
Any offer of employment for this position is also contingent on the Company verifying that you are a authorized for access to export-controlled technology under applicable export control laws or, if you are not already authorized, our ability to successfully obtain any necessary export license(s) or other approvals.
SiFive is an equal opportunity employer. We celebrate diversity and are committed to creating an inclusive environment for all employees.
Top Skills
What We Do
The heart of SiFive is RISC-V! SiFive creates the building blocks of RISC-V-based IP that are the inevitable innovative reimagining of every computing platform.
