About Marvell
Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities.
At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead.
Your Team, Your Impact
About MarvellMarvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities.
At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead.
Your Team, Your Impact
Built on decades of expertise and execution, Marvell’s custom Processor/ASIC solution offers a differentiated approach with a best-in-class portfolio of data infrastructure intellectual property (IP) and a wide array of flexible business models. In this unique role, you’ll have the opportunity to work on both the physical design and methodology for future designs of our next-generation, high-performance processor chips in a leading-edge CMOS process technology, targeted at server, and networking applications.
What You Can Expect
As a senior technical contributor in the central physical design team, you will:
Drive improvements in physical design methodologies, flows, and automation to enhance productivity, PPA, and signoff quality
Own RTL‑to‑GDSII implementation for complex blocks or partitions, including synthesis, floorplanning, PnR, CTS, timing closure, IR/EM/crosstalk analysis, and physical verification (DRC/LVS)
Solve complex technical challenges across congestion, timing, signal‑integrity, and design‑rule issues, partnering closely with RTL, STA, and verification teams
Collaborate cross‑functionally to influence design decisions, constraints, and micro‑architecture choices that improve physical feasibility
Guide and mentor junior engineers, sharing best practices and helping elevate engineering capability across the organization
Contribute to next‑generation design methodologies and help evaluate new tools, technologies, and automation opportunities
Work closely with global timing and architecture teams to debug and resolve block‑level and subsystem‑level timing issues
Engage with EDA vendors to drive tool enhancements and participate in evaluations of new features or flows
What We're Looking For
Bachelor’s degree in Computer Science, Electrical Engineering or related fields and 5-10 years of related professional experience or Master’s degree and/or PhD in Computer Science, Electrical Engineering or related fields with 3-5 years of experience or equivalent professional experience in lieu of a formal degree.
Proven ability to drive physical design execution for large, high‑performance chips and contribute to successful, high‑quality tape outs under aggressive schedules
Deep expertise in hierarchical physical design strategies, advanced-node implementation challenges, and industry‑standard methodologies
In‑depth understanding of current foundry technologies and design constraints
Strong understanding of the ASIC design flow, including RTL integration, synthesis, PnR, timing closure, and signoff
Expert-level knowledge of modern EDA tools and flows across implementation, analysis, and verification
Proficiency in automation and scripting using Makefile, Tcl, Python, or Perl to improve flow robustness and efficiency
Strong communication and collaboration skills, with the ability to influence and work effectively across cross‑functional engineering teams
Experience contributing to the development and deployment of advanced physical design methodologies and flows
Strong knowledge of static timing analysis (PrimeTime, Tempus), EM/IR‑drop and crosstalk analysis (PTSI, Voltus, Redhawk, PrimeRail), extraction tools (Quantus, StarRC), and formal/physical verification tools (Formality, Verplex, Calibre, Hercules). (Experience with all tools is not required but is a strong plus.)
Familiarity with AI/ML‑driven optimization in physical design tools is a plus
Expected Base Pay Range (USD)
173,800 - 257,190, $ per annumThe successful candidate’s starting base pay will be determined based on job-related skills, experience, qualifications, work location and market conditions. The expected base pay range for this role may be modified based on market conditions.
Additional Compensation and Benefit Elements
Marvell is committed to providing exceptional, comprehensive benefits that support our employees at every stage - from internship to retirement and through life’s most important moments. Our offerings are built around four key pillars: financial well-being, family support, mental and physical health, and recognition. Highlights include an employee stock purchase plan with a 2-year look back, family support programs to help balance work and home life, robust mental health resources to prioritize emotional well-being, and a recognition and service awards to celebrate contributions and milestones. We look forward to sharing more with you during the interview process.All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.
Any applicant who requires a reasonable accommodation during the selection process should contact Marvell HR Helpdesk at [email protected].
Interview Integrity
To support fair and authentic hiring practices, candidates are not permitted to use AI tools (such as transcription apps, real-time answer generators like ChatGPT or Copilot, or automated note-taking bots) during interviews.
These tools must not be used to record, assist with, or enhance responses in any way. Our interviews are designed to evaluate your individual experience, thought process, and communication skills in real time. Use of AI tools without prior instruction from the interviewer will result in disqualification from the hiring process.
This position may require access to technology and/or software subject to U.S. export control laws and regulations, including the Export Administration Regulations (EAR). As such, applicants must be eligible to access export-controlled information as defined under applicable law. Marvell may be required to obtain export licensing approval from the U.S. Department of Commerce and/or the U.S. Department of State. Except for U.S. citizens, lawful permanent residents, or protected individuals as defined by 8 U.S.C. 1324b(a)(3), all applicants may be subject to an export license review process prior to employment.
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What We Do
Marvell specializes in semiconductor solutions that power a wide range of industries, from data centers and 5G networks to AI, automotive, and storage applications. Our cutting-edge products are designed to meet the constantly evolving demands of a connected world, enabling faster, more efficient and more secure data processing and communication. With a focus on excellence and a commitment to advancing technology, we develop solutions that drive progress and transform industries.
Why Work With Us
Life at Marvell means being a part of new innovation and enduring technology; but it's also much more. Our diverse community is strengthened through cultural events, corporate gatherings and team-building activities, fostering collaboration and making work enjoyable. At Marvell, it's not just a job; it's an enriching, community-driven experience.
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