Principal Physical Design Engineer (ICB5)

Posted 2 Days Ago
Be an Early Applicant
Innovation, VA
141K-225K Annually
Senior level
Semiconductor
The Role
The Principal Physical Design Engineer will oversee high-speed physical designs, including floorplanning, physical implementation, verification, and timing closure. The role requires collaborating with multiple teams to ensure effective design methodologies and confronting challenges such as timing closure and congestion resolution. Strong problem-solving skills and proficiency with design tools are necessary.
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Job Description:

The Network Switch Group at Broadcom Inc. has brought some of the most complex and cutting edge networking ASIC's and multi-chip solutions to market over the last decade. These products support the latest networking protocols and features as well as manage extremely large volumes of internet traffic.

 

As a Senior Physical Design Engineer, the ideal candidate will be responsible for the 3nm high speed physical designs. You will be directly involved in:

· Floorplanning including multi-power domain, PG planning etc.

. Physical implementation of blocks and top-level including clock-tree.

·  Physical verification and timing closure for block and chip-level.

. Static and dynamic IR drop analysis, signal and power EM checks.

·   Methodology & Flow development of Physical Design and Timing Closure.

.  Interfacing with internal and external teams including Design, IP, Library.

Candidate should be well experienced in floor-planning, partitioning, placement, clock tree synthesis, route and physical verification. Should have excellent problem solving skill to help through congestion resolution and timing closure. Should have experience of formal verification and timing analysis and Eco implementation. Should be able to work independently and help other team members. Should possess ability to learn and adapt to new tools and methodologies. Excellent communication skill is a must. Experience with tools such as Innovus, Calibre, LEC, PrimeTime etc is highly desirable. Full chip tapeout experience based on 3nm technologies is preferred.

BE plus 12+ years, or ME plus 10+ years, in deep-sub-micron IC physical designs, or equivalent experience
Experience with TCL and Perl, to achieve higher productivity, is desired

Additional Job Description:

Compensation and Benefits

The annual base salary range for this position is $141,000 - $225,000

This position is also eligible for a discretionary annual bonus in accordance with relevant plan documents, and equity in accordance with equity plan documents and equity award agreements.

Broadcom offers a competitive and comprehensive benefits package: Medical, dental and vision plans, 401(K) participation including company matching, Employee Stock Purchase Program (ESPP), Employee Assistance Program (EAP), company paid holidays, paid sick leave and vacation time. The company follows all applicable laws for Paid Family Leave and other leaves of absence.

Broadcom is proud to be an equal opportunity employer. We will consider qualified applicants without regard to race, color, creed, religion, sex, sexual orientation, gender identity, national origin, citizenship, disability status, medical condition, pregnancy, protected veteran status or any other characteristic protected by federal, state, or local law. We will also consider qualified applicants with arrest and conviction records consistent with local law.

If you are located outside USA, please be sure to fill out a home address as this will be used for future correspondence.

Top Skills

Perl
Tcl
The Company
HQ: San Jose, CA
38,985 Employees
On-site Workplace
Year Founded: 1991

What We Do

Broadcom Inc. (NASDAQ: AVGO) is a global technology leader that designs,
develops and supplies semiconductor and infrastructure software solutions.

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