Microsoft Silicon, Cloud Hardware, and Infrastructure Engineering (SCHIE) is the team behind Microsoft’s expanding Cloud Infrastructure and responsible for powering Microsoft’s “Intelligent Cloud” mission. SCHIE delivers the core infrastructure and foundational technologies for Microsoft's over 200 online businesses including Bing, MSN, Office 365, Xbox Live, Teams, OneDrive, and the Microsoft Azure platform globally with our server and data center infrastructure, security and compliance, operations, globalization, and manageability solutions. Our focus is on smart growth, high efficiency, and delivering a trusted experience to customers and partners worldwide and we are looking for engineers to help achieve that mission.
As Microsoft's cloud business continues to accelerate, the ability to deliver new silicon innovations and infrastructure at scale, with quality, speed, and cost efficiency, has never been more critical. Within SCHIE, the Methodology, Infrastructure & Labs Engineering (MILE) organization plays a pivotal role in enabling Microsoft's silicon strategy. MILE is responsible for end-to-end silicon design methodologies, EDA/CAD ecosystems, and the underlying compute infrastructure that powers the development of Microsoft's custom silicon portfolio - the Azure Cobalt and Azure Maia processors
We are seeking a Principal PD CAD Engineer to be the technical lead in our Physical Design Methodology & CAD team in India. In this leadership role, you will build and be responsible in defining and driving end to end physical design methodologies, with a focus on PD construction space, define CAD strategy, and flow architecture across Microsoft's silicon programs. You will partner closely with engineering teams worldwide to deliver scalable, innovative, and robust solutions that accelerate silicon development and help shape the future of Microsoft's cloud infrastructure.
Responsibilities
Build world-class Physical Design Methodologies & CAD solutions fostering innovation, technical excellence, and a growth mindset.
Partner with engineering leaders worldwide to define and execute the long-term vision for Physical Design methodologies and CAD solutions, enabling multi-vendor solutions and successful delivery of Microsoft's next-generation silicon products.
Drive scalable RTL-to-GDSII flows, automation frameworks, and design closure solutions that enable predictable execution and first-pass silicon success.
Lead the AI-driven transformation of physical design methodologies, CAD flows, and engineering infrastructure by integrating advanced AI, machine learning, and automation technologies to significantly improve productivity, quality, and engineering velocity.
Influence industry direction through deep collaboration with leading EDA vendors, driving next-generation design technologies, methodology innovation, and operational excellence across Microsoft's silicon ecosystem.
Champion measurable improvements in quality, productivity, compute efficiency, cost optimization, and engineering effectiveness across the silicon development lifecycle.
Qualifications
Required Qualifications:
Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field.
12+ years technical engineering experience OR equivalent experience in Physical Design, CAD, EDA, or Silicon Engineering, with deep expertise in semiconductor design methodologies and workflows.
Proven experience defining, building, and scaling CAD methodologies, automation frameworks, and engineering workflows supporting complex SoC and ASIC development programs.
Proven success influencing and aligning stakeholders across globally distributed engineering teams to drive cross-functional initiatives and deliver complex silicon programs.
Demonstrated impact driving engineering excellence through hands on experience in methodology, automation, infrastructure, and tooling that improve productivity, quality, predictability, and time-to-market.
Other Requirements:
Ability to meet Microsoft, customer, and/or government security screening requirements is required for this role. These requirements include, but are not limited to, the following specialized security screening:
Microsoft Cloud Background Check. This position is required to pass the Microsoft Cloud Background Check upon hire or transfer and every two years thereafter.
This role will require access to information that is controlled for export under export control regulations, potentially under the U.S. International Traffic in Arms Regulations or Export Administration Regulations, the EU Dual Use Regulation, and/or other export control regulations. As a condition of employment, the successful candidate will be required to provide either proof of their country of citizenship or proof of their U.S. permanent residency or other protected status (e.g., under 8 U.S.C. 1324b(a)(3)) for assessment of eligibility to access the export-controlled information. To meet this legal requirement, and as a condition of employment, the successful candidate’s citizenship will be verified with a valid passport. Lawful permanent residents, refugees, and asylees may verify status using other documents, where applicable.
Preferred Qualifications:
Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field with 15+ years of relevant experience
Deep expertise in RTL-to-GDSII implementation and sign-off methodologies
Experience leading Physical Design methodology and supporting multiple silicon programs.
Experience driving AI-enabled, data-driven, or automation-focused transformation initiatives within silicon engineering workflows.
Hands-on experience building and scaling compute infrastructure, cloud-native engineering platforms, or large-scale EDA environments.
Strong knowledge of industry-standard EDA tools and methodologies from vendors such as Synopsys, Cadence, and Siemens.
Experience partnering with EDA vendors to influence product roadmaps, drive tool adoption, and resolve complex technical challenges.
Strong programming and automation skills using Python, Tcl, Perl, Shell, or similar languages.
Experience developing silicon for datacentre, AI/ML, networking, or high-performance computing applications.
This position will be open for a minimum of 5 days, with applications accepted on an ongoing basis until the position is filled.
Microsoft is an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to age, ancestry, citizenship, color, family or medical care leave, gender identity or expression, genetic information, immigration status, marital status, medical condition, national origin, physical or mental disability, political affiliation, protected veteran or military status, race, ethnicity, religion, sex (including pregnancy), sexual orientation, or any other characteristic protected by applicable local laws, regulations and ordinances. If you need assistance with religious accommodations and/or a reasonable accommodation due to a disability during the application process, read more about requesting accommodations.
Skills Required
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field
- 12+ years of technical engineering experience or equivalent experience in Physical Design, CAD, EDA, or Silicon Engineering
- Experience defining, building, and scaling CAD methodologies, automation frameworks, and engineering workflows for complex SoC and ASIC development
- Experience influencing globally distributed engineering stakeholders and delivering cross-functional silicon programs
- Hands-on experience in methodology, automation, infrastructure, and tooling improvements
- Ability to meet Microsoft Cloud Background Check and other applicable security screening requirements
- Citizenship, permanent residency, or other protected-status verification for access to export-controlled information
- Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field with 15+ years of relevant experience
- Deep expertise in RTL-to-GDSII implementation and sign-off methodologies
- Experience leading Physical Design methodology across multiple silicon programs
- Experience driving AI-enabled, data-driven, or automation-focused transformation in silicon engineering workflows
- Experience building and scaling compute infrastructure, cloud-native engineering platforms, or large-scale EDA environments
- Knowledge of industry-standard EDA tools and methodologies from Synopsys, Cadence, and Siemens
- Experience partnering with EDA vendors to influence product roadmaps, drive tool adoption, and resolve technical challenges
- Programming and automation experience using Python, Tcl, Perl, Shell, or similar languages
- Experience developing silicon for datacenter, AI/ML, networking, or high-performance computing applications
Microsoft Compensation & Benefits Highlights
The following summarizes recurring compensation and benefits themes identified from responses generated by popular LLMs to common candidate questions about Microsoft and has not been reviewed or approved by Microsoft.
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Healthcare Strength — Medical, dental, and vision coverage is described as comprehensive, with U.S. plans covering preventive care at 100% and limiting annual out-of-pocket costs. Mental-health counseling, employee assistance, and wellbeing resources are also emphasized.
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Parental & Family Support — Parental leave, family-caregiver leave, childcare assistance, and family concierge services are highlighted as core elements. These supports are presented alongside parenting and family-planning resources.
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Leave & Time Off Breadth — Vacation, holidays, and flexible work schedules are emphasized, with generous time-away policies noted. Leave options extend beyond standard vacation to include caregiver and parental programs.
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