Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions grounded in open standards. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. Discover more at www.asteralabs.com.
Job Description:
The mission of this role is to architect and develop firmware and microcontroller subsystems for Astera Labs’ SoC and systems products. Firmware is responsible for implementing the major differentiating features of Astera Labs’ products. As such, firmware is considered equally important to the hardware, and the firmware team is often customer-facing accordingly to ensure the needs of the customer are fully comprehended.
Basic Qualifications:
- Strong academic and technical background in electrical engineering. At a minimum, a Bachelor’s in EE or Computer Science is required.
- Minimum 10 years’ Firmware experience developing firmware to execute in on-chip microcontrollers as well as C-language Software Development Kits (SDKs) to execute on system host CPUs and embedded microprocessors.
- Minimum 2 years of OpenBMC experience including design, configuration, development, build, debug, deployment and support.
- Minimum 2 year experience with RedFish, RDE, PLDM, SPDM, MCTP
- Experience working with logic designers to implement and test HW-SW interfaces on complex SoCs.
- Professional attitude with the ability to prioritize a dynamic list of multiple tasks, and to work with minimal guidance and supervision.
- Entrepreneurial, open-minded behavior and can-do attitude. Think and act fast with the customer in mind!
- Authorized to work in Canada and start immediately.
Required Experience:
- High level of proficiency in C or C++.
- Proficient in Python for scripting.
- Ability to design, implement, and write unit-level tests.
- Working knowledge of software build environments such as gcc, make or cmake.
- Experience with developer workflows, SCM (preferably git), code reviews, CI/CD.
- Hands-on experience with Server, Storage, and/or Networking equipment.
- Familiarity with SoC interfaces to common IP blocks such as PCIe Controllers, DDR Controllers, NVME Controllers, on-chip memory interfaces, and other similar interfaces.
Preferred Experience:
- Experience with additional DMTF standards is an asset.
- RTOS development experience is an asset.
- Pre-silicon emulation development experience is an asset.
- Experience with PCIe/CXL firmware development and lab debug is an asset.
- Experience developing firmware for PCIe or Ethernet Switch products is an asset.
The base salary range is $180,000.00 CDN – $240,000.00 CDN. Your base salary will be determined based on your location, experience, and the pay of employees in similar positions.
We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.
Top Skills
What We Do
Astera Labs Inc., a fabless semiconductor company headquartered in the heart of California’s Silicon Valley, is a leader in purpose-built connectivity solutions for data-centric systems throughout the data center.
Partnering with leading processor vendors, cloud service providers, seasoned investors, and world-class manufacturing companies, Astera Labs is helping customers remove performance bottlenecks in data-intensive systems that are limiting the true potential of applications such as artificial intelligence and machine learning.
The company’s product portfolio includes system-aware semiconductor integrated circuits, boards, and services to enable robust CXL, PCIe, and Ethernet connectivity.
