Principal Engineer-ASIC Design (Integration)

Are you looking for a unique opportunity to be a part of something great? Want to join a 20,000-member team that works on the technology that powers the world around us? Looking for an atmosphere of trust, empowerment, respect, diversity, and communication? How about an opportunity to own a piece of a multi-billion dollar (with a B!) global organization? We offer all that and more at Microchip Technology, Inc.

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Job Description:

Summary

As a member of Microchip's engineering community, your primary responsibility will be to the design, integration, and verification support of the Full Chip Architecture and Full Chip Control/Data busses for an advanced ASIC or FPGA. Microchip's designs are an SOC with various Hard and Soft IP blocks that support many industry standard protocols.

Duties & Responsibilities

General Full Chip Integration and Support

• Detailed module design and integration, performance analysis and detailed design specification creation - a large component of this position is to work with all design teams to ensure seamless integration of all components on the device.
• Detailed ownership of full chip documentation of the SOC or FPGA device and/or device family.
• Participate in the Verilog implementation and integration of full chip capabilities including interface support, integration of full chip busses (control and data network-on-chip) and documentation support at the full chip level.
• Support full chip post-layout timing closure and verification.
• Participate in the investigation & assessment of legacy and emerging integration techniques and on-chip / off-chip network-on-chip (NOC) bus structures for both control and high-speed data paths. Overall support of the full chip register map at the chip level is required.
• Improve Data & Command processing bandwidth, reduce latencies & increase reliability.
• Support porting the design into test chips and emulation platforms
• Support pre-tapeout verification and post-tapeout validation/characterization of the system designed.
• Work closely with FPGA support software and Firmware engineers to resolve hardware issues and customer issues.

Requirements/Qualifications:

• Experience is SOC IP development and Full Chip Integration
• Strong technical leader that is also able to work in a team-oriented environment.
• Strong Experience in Verilog design and design verification
• Strong Experience in Static Timing Analysis and Verilog simulation tools
• Ability to write detailed design specifications.
• Good analytical, oral, and written communication skills.
• Able to write clean, readable presentations.
• Self-motivated, proactive team player.
• Ability to work to schedule requirements.

Education Required

• Bachelors/master's in electrical engineering, Computer Engineering or Computer Science.

Experience Required

• Minimum of 10 years of proven silicon design experience in system level integration of many different internally developed and purchased full custom and ASIC IP blocks into a full chip environment. This would also include the integration of control and high-speed data network-on-chip (NOC) busses.

U.S. Export Controls Requirements: This job requires access to technology, materials, software or hardware that is controlled by the export laws of the United States. Candidates are required to provide proof of either US citizenship, Permanent US residency or classification as a protected individual as defined in 8 USC 1324b (a) (3).

Travel Time:

0% - 25%

Physical Attributes:

Hearing, Seeing, Talking, Works Alone, Works Around Others

Physical Requirements:

100% inside, 80 % sitting, 10% standing, 10% walking

Microchip Technology Inc is an equal opportunity/affirmative action employer. All qualified applicants will receive consideration for employment without regard to sex, gender identity, sexual orientation, race, color, religion, national origin, disability, protected Veteran status, age, or any other characteristic protected by law.

For more information on applicable equal employment regulations, please refer to the EEO is the Law Poster and the EEO is the Law Poster Supplement. Please also refer to the Pay Transparency Policy Statement.