Principal Electrical Engineer

Posted 4 Hours Ago
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Palo Alto, CA, USA
Hybrid
180K-240K Annually
Senior level
Artificial Intelligence • Hardware • Semiconductor
Stronger Network. Faster Inference.
The Role
Lead board‑level and system architecture for server and data‑center compute platforms. Drive schematic design, component selection, power delivery, high‑speed interface requirements, validation/bring‑up, and manufacturing readiness. Engage Taiwan ODMs and customers, coordinate SI/PI, firmware, mechanical, and packaging teams, and support production builds and issue resolution.
Summary Generated by Built In

Senior Electrical Engineer

 

Who We Are

We are a stealth‑mode startup building foundational technology to address performance, scalability, and resiliency challenges in large‑scale AI data center clusters. We are backed by top‑tier VC firms and notable angel investors. The company is led by experienced builders and operators who have founded companies, taken them to scale, and exited successfully. We work with a strong sense of unity and shared responsibility, and we expect trust, integrity, and respect in how we collaborate and make decisions. We hold ourselves accountable to one another and to the quality of the work we deliver. Headquartered in Silicon Valley, we operate across a mix of remote and on‑site locations in the U.S., Canada, and Taiwan. We aim to create an environment where people are treated fairly, supported in their growth, and empowered to do meaningful work alongside others who take the craft seriously.

Some Recent Press: https://www.eetimes.com/startup-boosts-scale-up-to-1000-gpus-in-a-single-domain/

 

What We Need

We are seeking a Senior Electrical Engineer with deep experience in board‑level design, system architecture, and server/data‑center hardware development. This role will drive board design execution, system integration, and technical engagement with ODMs and customers to deliver high‑performance compute platforms.

 

Key Responsibilities

  • Board Architecture & Design — Lead schematic design, component selection, and power‑tree definition for complex server and data‑center boards.

  • System‑Level Design — Define system architecture, high‑speed interface requirements, power delivery strategy, and thermal/mechanical constraints.

  • Data Center & Server Hardware — Develop boards and systems supporting CPUs, accelerators, memory subsystems, high‑speed IO, and advanced power architectures.

  • ODM Engagement — Work closely with Taiwan ODMs on design reviews, issue resolution, schedule alignment, and manufacturing readiness.

  • Customer Interaction — Support customer technical discussions, requirements gathering, and design‑in activities.

  • High‑Speed Interfaces — Collaborate with SI/PI teams to ensure compliance for PCIe, CXL, Ethernet, UCIe, CPO, and other high‑speed links.

  • Validation & Bring‑Up — Lead board bring‑up, debug, and system‑level validation using scopes, logic analyzers, and protocol analyzers.

  • Cross‑Functional Collaboration — Partner with packaging, SI/PI, firmware, and mechanical teams to deliver fully integrated systems.

  • Manufacturing Support — Drive DFM/DFT reviews, support factory builds, and resolve production issues with ODM partners.

     

Required Skills & Qualifications

  • B.S./M.S. in Electrical Engineering or related field.

  • 8+ years of experience in board design and system‑level hardware development.

  • Strong background in server, data‑center, or high‑performance compute platforms.

  • Expertise in schematic capture, power architecture, and high‑speed digital design.

  • Experience working directly with Taiwan ODMs (Quanta, Wistron, Inventec, Foxconn, etc.).

  • Familiarity with PCIe, CXL, DDR, Ethernet, CPO, and other high‑speed interfaces.

  • Hands‑on experience with lab equipment (oscilloscopes, logic analyzers, protocol analyzers).

  • Ability to lead cross‑functional technical discussions with customers and partners.

  • Knowledge of SI/PI fundamentals is a plus.

  • Experience with server‑class power delivery (VRMs, multiphase regulators) is a plus.

Compensation

Target base salary for this role is $180,000–$240,000 per year + meaningful equity + benefits + 401k. Our salary ranges are determined by role, level, experience, and location.

We are an equal opportunity employer. We value a range of perspectives and experiences and make employment decisions based on merit and business needs. We do not discriminate on the basis of legally protected characteristics.

Agency Note:

We do not accept resumes from agencies or search firms. Please do not forward candidate profiles through our careers page, email, LinkedIn messages, or directly to company employees. Any resumes submitted will be deemed the property of the company, and no fees will be paid in the event the candidate is hired.

  •  

Skills Required

  • B.S./M.S. in Electrical Engineering or related field.
  • 8+ years of experience in board design and system-level hardware development.
  • Strong background in server, data-center, or high-performance compute platforms.
  • Expertise in schematic capture, power architecture, and high-speed digital design.
  • Experience working directly with Taiwan ODMs (Quanta, Wistron, Inventec, Foxconn, etc.).
  • Familiarity with PCIe, CXL, DDR, Ethernet, CPO, and other high-speed interfaces.
  • Hands-on experience with lab equipment (oscilloscopes, logic analyzers, protocol analyzers).
  • Ability to lead cross-functional technical discussions with customers and partners.
  • Knowledge of SI/PI fundamentals.
  • Experience with server-class power delivery (VRMs, multiphase regulators).
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The Company
50 Employees
Year Founded: 2025

What We Do

We are a mixture of software, system, and silicon experts using AI every day to deliver the world's most capable and responsive intelligence.

Why Work With Us

We are a mixture of software, system, and silicon experts using AI every day to deliver the world's most capable and responsive intelligence. We start from the workload. Scaling inference is less about brute force and more about how compute is distributed and memory is interc

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