Principal Digital Design Engineer

Posted Yesterday
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Toronto, ON, CAN
In-Office
Senior level
Big Data • Information Technology
The Role
Lead architecture, RTL implementation, and integration of high-performance PCIe/Ethernet/SerDes digital blocks through full-chip design at ≤16nm. Drive timing closure, verification, pre/post-silicon bring-up, IP integration, DFT, and use Synopsys/Cadence tooling while collaborating with cross-functional teams and firmware engineers.
Summary Generated by Built In

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com.

Job Description 

We are seeking a Principal Digital Design Engineer with deep expertise in high-performance PCIE or Ethernet controller and bridge or switch design, micro-architecture, RTL implementation, and IP integration. The ideal candidate will play a critical role in the development of cutting-edge connectivity solutions. 

Key Responsibilities: 

  • Design and implement high-performance digital solutions, including RTL development and synthesis. 
  • Collaborate with cross-functional teams on IP integration for Serdes and Controller IPS, processor and peripherals 
  • Own block-level and full-chip designs from architecture to GDS, focusing on designs at nodes ≤ 16nm. 
  • Ensure timing closure, assess verification completeness, CDC, lint etc. 
  • Utilize tools from Synopsys/Cadence for design and emulation. 

Basic Qualifications: 

  • Bachelor’s in Electronics/Electrical engineering (Master's preferred). 
  • +8 years of digital design experience, with 4+ years focused on PCIE or Ethernet controller, PCS or PHY implementation. 
  • Proven expertise in RTL development, synthesis, and timing closure. 
  • Experience with front-end design, gate-level simulations, and design verification. 
  • Strong work ethic, ability to handle multiple tasks, and a proactive, customer-focused attitude. 

Required Expertise: 

  • Hands-on experience with PCIE or Ethernet Controller or Serdes/PHY IP. 
  • Hands-on pre-silicon and post-silicon design implementation. 
  • Hands-on experience  FW interaction and embedded design. 
  • Strong proficiency in System Verilog/Verilog and scripting (Python/Perl). 
  • Experience with block-level and full-chip design at advanced nodes (≤ 16nm). 
  • Top level integration and DFT knowledge. 

Preferred Experience: 

  • PCIE or Ethernet SerDes controller or IP level experience. 
  • Understanding of PAD design, DFT, and floor planning. 
  • Experience with NIC, switch, or storage product development including embedded FW. 
  • Familiarity with working in design and verification workflows in a CI/CD environment. 

We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.

Skills Required

  • Bachelor's in Electronics/Electrical Engineering
  • Master's degree in relevant field
  • 8+ years digital design experience with 4+ years focused on PCIe or Ethernet controller, PCS or PHY implementation
  • Hands-on experience with PCIe or Ethernet Controller or SerDes/PHY IP
  • RTL development, synthesis, and timing closure expertise
  • Front-end design, gate-level simulations, and design verification experience
  • Pre-silicon and post-silicon design implementation experience
  • Embedded firmware interaction and embedded design experience
  • Proficiency in SystemVerilog/Verilog
  • Scripting experience (Python or Perl)
  • Block-level and full-chip design experience at advanced nodes (≤ 16nm)
  • Top-level integration and DFT knowledge
  • Experience using Synopsys/Cadence tools for design and emulation
  • Experience with CDC, lint, and verification completeness assessment
  • PCIE or Ethernet SerDes controller or IP-level experience
  • Understanding of PAD design and floor planning
  • Experience with NIC, switch, or storage product development including embedded firmware
  • Familiarity with CI/CD workflows for design and verification
  • Strong work ethic, multitasking ability, proactive and customer-focused attitude
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The Company
HQ: Santa Clara, CA
148 Employees
Year Founded: 2017

What We Do

Astera Labs Inc., a fabless semiconductor company headquartered in the heart of California’s Silicon Valley, is a leader in purpose-built connectivity solutions for data-centric systems throughout the data center. Partnering with leading processor vendors, cloud service providers, seasoned investors, and world-class manufacturing companies, Astera Labs is helping customers remove performance bottlenecks in data-intensive systems that are limiting the true potential of applications such as artificial intelligence and machine learning. The company’s product portfolio includes system-aware semiconductor integrated circuits, boards, and services to enable robust CXL, PCIe, and Ethernet connectivity.

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