The Allegro team is united by a clear purpose—advancing technologies that make the world safer, more efficient, and more sustainable. With over 30 years of experience in semiconductor innovation, we bring that purpose to life across every part of the business—from breakthrough product development and customer success to how we show up for each other and the communities we serve.
ROLE OVERVIEW
In this position, you will be a technical leader within a multi-site, growing, and dynamic team, defining and driving the digital architecture for our industry-leading mixed-signal motor drive ICs. You will be responsible for leading the architecture, design, and verification strategy for a wide range of complex digital solutions, from standalone IP to full System-on-Chip (SoC) designs. This role will provide you with the opportunity to influence the technical direction and solve the most challenging problems in automotive motor control.
RESPONSIBILITIES
Lead the definition of system-level requirements and own the digital architecture for complex digital solutions, including both IP-level and full SoC architectures.
Architect and lead the implementation of complex, reusable RTL modules and top-level chip integration using Verilog, ensuring adherence to best practices for low-power and high-performance design.
Own and drive the evolution of the digital design methodology, identifying, evaluating, and deploying new tools and best practices to enhance efficiency and quality.
Oversee the FPGA validation and pre-silicon emulation strategy, ensuring robust verification of the entire system and seamless interface between hardware and software.
Support the overall verification strategy in collaboration with the verification team, defining success criteria, and ensuring comprehensive functional coverage to deliver first-pass silicon success.
Collaborate with the physical implementation team to resolve critical timing, power, and area challenges on advanced technology nodes.
Mentor junior and senior engineers, fostering technical growth and excellence within the digital design team.
KEY RELATIONSHIPS
Internal
Act as a technical authority, collaborating with and guiding digital design and verification engineers.
Serve as the primary technical interface to the physical implementation, systems, software, and applications teams.
Partner with systems engineers and marketing to define next-generation product requirements and technical roadmaps.
Provide expert guidance to test engineers on the development of robust ATPG and production test programs.
External
Lead technical discussions with key customers and off-site design teams.
Drive technical engagements with EDA and IP vendors to influence their roadmaps and resolve critical issues.
PERSON SPECIFICATION
Qualifications
Essential: Prospective candidates must have a PhD or Master's degree (or equivalent) in Electronics or a related field, combined with extensive, proven experience in a senior or principal digital design role.
Skills, Knowledge, and Aptitudes
Essential:
Expert-level knowledge of digital architectures, ranging from complex algorithmic IP to full SoC designs including CPU subsystems, interconnect fabrics (e.g., AMBA/AXI), and system-level protocols.
Proven track record of leading complex digital architecture and integration (IP and/or SoC), from specification through to tape-out and silicon validation.
Mastery of advanced digital design principles, including low-power and high-speed design techniques.
Deep understanding and practical application of advanced DFT/DFM techniques, including scan compression, boundary scan, and memory BIST.
Expertise in advanced FPGA prototyping and emulation techniques for complex digital systems.
Recognized technical leader with the ability to influence and guide cross-functional teams and make critical technical trade-offs.
Demonstrated ability to mentor and develop other engineers.
Exceptional verbal and written communication skills, with the ability to present complex technical concepts to a wide range of audiences.
Desirable:
Expertise with Cadence or equivalent EDA toolsets for the entire front-end design and verification flow.
Experience with functional safety standards such as ISO 26262.
TRAVEL REQUIREMENTS
Domestic and international travel may be required for this role. The below provides an indication only of the amount, type, and locations of travel. This is subject to change depending on business requirements.
National Travel: 5-10%
International Travel: 5-10%
Travel Locations: Dependent on work that may arise, most likely travel will be within Europe, the Americas, and Asia.
Why Allegro?
Join Allegro and become part of a team where your contributions truly matter.
We foster a culture of Real Innovation, empowering you to push boundaries, develop cutting-edge solutions, and drive continuous improvement.
Your work will create a Real Impact by solving complex real-world challenges that fuel our success and shape the future of technology.
You’ll experience Real Connection, collaborating with talented colleagues around the globe in an environment built on trust, respect, and a shared purpose.
Join us—and help build what’s next.
Skills Required
- PhD or Master's degree, or equivalent, in Electronics or a related field
- Extensive, proven experience in a senior or principal digital design role
- Expert knowledge of digital architectures spanning algorithmic IP, full SoC designs, CPU subsystems, AMBA/AXI interconnects, and system-level protocols
- Experience leading complex digital architecture and integration from specification through tape-out and silicon validation
- Mastery of low-power and high-speed digital design techniques
- Advanced DFT/DFM expertise, including scan compression, boundary scan, and memory BIST
- Advanced FPGA prototyping and emulation experience for complex digital systems
- Technical leadership, cross-functional influence, and ability to make critical technical trade-offs
- Ability to mentor and develop engineers
- Exceptional verbal and written communication skills
- Expertise with Cadence or equivalent EDA toolsets for front-end design and verification
- Experience with functional safety standards such as ISO 26262
Allegro MicroSystems Compensation & Benefits Highlights
The following summarizes recurring compensation and benefits themes identified from responses generated by popular LLMs to common candidate questions about Allegro MicroSystems and has not been reviewed or approved by Allegro MicroSystems.
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Strong & Reliable Incentives — Feedback suggests bonuses are generous and a meaningful part of total compensation. Variable pay is viewed as reliably contributing to take-home pay.
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Healthcare Strength — Comprehensive medical, dental, vision, mental health, and fertility support is seen as robust. Day-one eligibility and advocacy services further strengthen access to care.
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Leave & Time Off Breadth — Vacation, sick/personal time, parental and family leave, holidays, and volunteer time off provide ample ways to step away from work. Generous PTO and floating holidays contribute to work-life balance.
Allegro MicroSystems Insights
What We Do
At Allegro MicroSystems, we’re passionate about developing intelligent solutions that move the world toward a safer and more sustainable future – while giving our customers a competitive edge. With more than 50 years of experience developing advanced semiconductor technology and application-specific algorithms, Allegro is a global leader in power and sensing solutions for motion control and energy-efficient systems. Through our innovations, we are helping our customers make breakthrough advancements in areas like advanced mobility, green energy, and factory automation. Each year, we ship over one billion units into these applications to support our 10,000+ customers around the globe, including over 50 automotive OEMs. Our diverse team of 3,500+ employees is spread across 13 countries, powering our global engineering, manufacturing, and support and enabling our innovations. That’s why we work hard to create a collaborative, energetic environment that rewards ingenuity and helps our employees make a difference every day.
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