Principal DFT Engineer

Posted 18 Days Ago
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Bengaluru, Bengaluru Urban, Karnataka, IND
In-Office
Expert/Leader
3D Printing
The Role
Owns end-to-end design-for-test architecture, implementation, verification, ATPG pattern generation, production-test readiness, and silicon bring-up for automotive MCU and SoC products. The role defines scan, compression, MBIST, LBIST, JTAG, and test-access strategies; drives DFT integration and coverage closure; validates patterns; investigates silicon and yield issues; and coordinates DFT requirements, sign-offs, milestones, and technical risks across design, verification, product, and test engineering teams.
Summary Generated by Built In
Company Description

Renesas is a global semiconductor leader shaping the backbone of next‑generation automotive, industrial, cloud, and IoT innovation. With over $9.3 billion in annual revenue (2024) and a world‑class team of 22,700+ employees, Renesas operates at scale while retaining the agility to drive category‑defining breakthroughs. The company’s footprint spans more than 30 countries, enabling deep customer proximity and a uniquely global innovative engine. As Japan’s semiconductor powerhouse and a top global player in microcontrollers, analog, and power technologies, Renesas delivers real‑world impact across EVs, smart factories, renewable energy infrastructure, and edge intelligence. For ambitious problem‑solvers who want to work on meaningful, systems‑level challenges with huge industry leverage, Renesas offers the scale, stability, and strategic clarity of a market leader—paired with the transformative momentum of a company reinventing how the world computes, connects, and electrifies.

Renesas has a growing presence in India with HC approaching 1000+ and significant presence with active government and university collaboration as well as OSAT footprint (JV with CG India). With the growing importance of India as a market (Growing semiconductor market and government goals / mandates of localization needs) and talent hub, our division’s (India for India) mission is to grow India market. We aspire to create products (SoCs, Software, Power and Analog chips etc) which serve needs for local market. Renesas is a leading electronics supplier globally, and this is a unique opportunity to directly influence the future products which will be offered to our customers in a new, fast growing and large Indian market with specific needs and applications.

Job Description

We are looking for an experienced DFT Lead to own end-to-end Design-for-Test activities for complex Automotive MCU/SoC products. The role will drive DFT architecture, implementation, verification, and production-test readiness while working closely with SoC Design, Verification, PTE, Product and Test Engineering teams.

Key Responsibilities

  • Own the DFT architecture and strategy for automotive MCU/SoC products from specification through silicon production readiness.
  • Define and implement DFT solutions including scan architecture, compression, memory BIST, logic BIST, boundary scan/JTAG and test access architecture, as applicable.
  • Drive DFT implementation and associated RTL/design updates, working closely with SoC, IP and RTL design teams.
  • Own DFT verification and simulation, including test-mode validation, scan/MBIST connectivity, ATPG-related simulations and gate-level verification.
  • Drive ATPG and pattern generation, validation and release of production-ready test patterns to Product and Test Engineering teams.
  • Act as the primary technical interface with PTE/Product/Test teams for DFT, test-pattern and silicon-test requirements.
  • Work with design teams to define and align DFT requirements, test modes, clocks, resets, power domains, constraints and chip-level integration requirements.
  • Review DFT coverage, pattern count, test time and testability metrics, and drive closure of coverage gaps.
  • Support silicon bring-up, pattern debug, test failures and yield-related DFT investigations.
  • Own DFT deliverables, reviews, sign-off criteria and milestone tracking across the product development lifecycle.
  • Identify DFT-related technical and schedule risks early and drive cross-functional closure.

Qualifications

Required Skills & Experience

  • 15+  year experience in DFT architecture and implementation for complex MCU/SoC devices.
  • Hands-on expertise in scan insertion, scan compression, ATPG, MBIST and JTAG/boundary scan.
  • Strong understanding of RTL and gate-level design, clocks, resets, power domains and SoC integration.
  • Experience with DFT simulation, pattern verification and gate-level simulation/debug.
  • Experience in ATPG pattern generation, fault coverage analysis and production pattern delivery.
  • Good understanding of the interface between design DFT and ATE/production testing.
  • Experience working with Product Engineering and Test Engineering teams during silicon bring-up and production ramp.
  • Familiarity with industry-standard DFT tool flows from Siemens EDA, Synopsys and/or Cadence.
  • Strong problem-solving and debugging skills with the ability to drive issues across multiple engineering organizations.
  • Ability to independently lead DFT activities and communicate effectively with architecture, design, verification, physical design and product/test teams.

Preferred Experience

  • Experience with automotive MCU or automotive SoC development.
  • Exposure to ISO 26262 / functional safety requirements and their impact on test architecture.
  • Experience with advanced DFT methodologies such as hierarchical test, embedded compression, logic BIST, repair/redundancy schemes or safety-oriented test features.
  • Understanding of production test cost, test time, coverage, diagnostic requirements and yield considerations.

What We Are Looking For

We are looking for someone who can take technical ownership of DFT, not just execute an established flow. The ideal candidate can make architecture decisions, work hands-on through implementation and verification, anticipate downstream production-test requirements, and effectively connect the design organization with Product and Test Engineering.

Additional Information

Renesas is an embedded semiconductor solution provider driven by its Purpose, To Make Our Lives Easier. With a global team of over 21,000 engineers and problem solvers in more than 30 countries, we offer the opportunity to work on world‑leading technology for Automotive, Industrial, Infrastructure, and IoT, shaping a safer, healthier, greener, and smarter future.

At Renesas, TAGIE is our culture, grounded in being Transparent, Agile, Global, Innovative, and Entrepreneurial. It shapes how we work, grow and deliver on our purpose together. This collaborative spirit and mindset drive our semiconductor technology to transform industries and impact millions of lives.

We believe in rewarding our employees with a competitive benefits package alongside their salary. More information will be provided during the hiring process.

Are you ready to join our team and shape the future with us?

Renesas Electronics is an equal opportunity and affirmative action employer, committed to supporting diversity and fostering a work environment free of discrimination on the basis of sex, race, religion, national origin, gender, gender identity, gender expression, age, sexual orientation, military status, veteran status, or any other basis protected by law. For more information, please read our Diversity & Inclusion Statement.

Skills Required

  • 15+ years of experience in DFT architecture and implementation for complex MCU or SoC devices
  • Hands-on expertise in scan insertion, scan compression, ATPG, MBIST, and JTAG or boundary scan
  • Strong understanding of RTL, gate-level design, clocks, resets, power domains, and SoC integration
  • Experience with DFT simulation, pattern verification, and gate-level simulation and debugging
  • Experience in ATPG pattern generation, fault coverage analysis, and production pattern delivery
  • Understanding of the interface between design DFT and ATE or production testing
  • Experience working with Product Engineering and Test Engineering teams during silicon bring-up and production ramp
  • Familiarity with industry-standard DFT tool flows from Siemens EDA, Synopsys, and/or Cadence
  • Strong problem-solving and debugging skills across multiple engineering organizations
  • Ability to independently lead DFT activities and communicate with architecture, design, verification, physical design, product, and test teams
  • Experience with automotive MCU or automotive SoC development
  • Exposure to ISO 26262 and functional safety requirements
  • Experience with hierarchical test, embedded compression, LBIST, repair and redundancy schemes, or safety-oriented test features
  • Understanding of production test cost, test time, coverage, diagnostic requirements, and yield considerations

Renesas Electronics Compensation & Benefits Highlights

The following summarizes recurring compensation and benefits themes identified from responses generated by popular LLMs to common candidate questions about Renesas Electronics and has not been reviewed or approved by Renesas Electronics.

  • Fair & Transparent Compensation — Feedback suggests pay is generally fair-to-good across many roles, with base pay aligned to prevailing market levels in multiple U.S. locations. Engineering and leadership tracks can be competitive on total compensation, reinforcing a sense that pay can meet market expectations in key job families.
  • Healthcare Strength — Feedback suggests core medical, dental, and vision coverage is solid and well-regarded by employees. Day-one eligibility in U.S. roles is described, supporting confidence in access and continuity of care.
  • Leave & Time Off Breadth — Feedback suggests PTO, paid holidays, sick time, and parental leave provide a comprehensive time-off framework. Company initiatives like Renesas Day and meeting-light Focus Fridays further support time away and balance.

Renesas Electronics Insights

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The Company
HQ: Tokyo
10,040 Employees

What We Do

We're the world's leading semiconductor manufacturer. Our mission is to make our lives easier and a world that's safer, healthier, greener, and smarter.

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