Staff, Design Verification Engineer, Fabric and Memory Subsystem

Experienced engineer focused on Fabric / Memory Subsystem verification for high-performance CPUs. The person coming into this role will work on a server class Fabric unit.

We have openings across multiple levels; once interviews have been completed, we will align your background with the appropriate engineering level.

This role is hybrid, based out of Boston, MA or Toronto, Ontario.

Responsibilities:

• Functional and performance verification of the Fabric unit for a from-scratch high performance CPU while working closely with Architecture and RTL team
• Develop detailed block level verification plans for a high-performance Fabric
• Design and develop reusable block level testbench components in SV, UVM and C++, that include microarchitectural models, monitors, checkers
• Develop random and directed stimulus that spans pre-silicon, emulation and post-silicon domain
• Evaluate and integrate open-source toolchains into the DV flow
• Develop DV environment, tools and infrastructure to enable functional verification for pre-silicon, emulation and post-silicon
• Work with design, test and post silicon validation teams to ensure high quality delivery of the Fabric / Mem Subsystem block

Experience and qualifications:

• BS/MS/PhD in EE/ECE/CE/CS with at least 5 years of experience
  Strong background and experience with high performance OOO CPU microarchitecture especially with load/store, caches and memory subsystem 
• Experience working on a Fabric for a CPU or GPU based system.  Knowledge of industry standard protocols such as CHI, AXI, ACE, Tilelink, CMN
• Architectural understanding of memory ordering, cache coherency protocols, memory consistency, multi-processors and fabric topologies
• Significant experience debugging RTL and DV in a simulation environment
• Verification methodologies and techniques – Simulation/debug, TB development, stimulus, checking, coverage, infrastructure, tools
• Experience with C++ / SV / UVM as well as scripting languages
• Experience with hardware description languages (Verilog, VHDL) and simulators (VCS, NC, Verilator)
• Strong problem solving and debug skills across various levels of design hierarchies

Compensation for all engineers at Tenstorrent ranges from $100k - $500k including base and variable compensation targets. Experience, skills, education, background and location all impact the actual offer made.

Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.

Due to U.S. Export Control laws and regulations, Tenstorrent is required to ensure compliance with licensing regulations when transferring technology to nationals of certain countries that have been licensing conditions set  by the U.S. government.

Our engineering positions and certain engineering support positions require access to information, systems, or technologies that are subject to U.S. Export Control laws and regulations, please note that citizenship/permanent residency, asylee and refugee information and/or documentation will be required and considered as Tenstorrent moves through the employment process.

If a U.S. export license is required, employment will not begin until a license with acceptable conditions is granted by the U.S. government.  If a U.S. export license with acceptable conditions is not granted by the U.S. government, then the offer of employment will be rescinded.