Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com.
Job Description
We are looking for a Principal Design Verification Engineer with proven experience in all aspects of verification in UVM and C/C++. The candidate must have experience using high level programming languages such as C/C++ to communicate with System Verilog and/or UVM based environments to aid RTL simulation, CoSimulation and Emulation.
Basic Qualifications:
- Strong academic and technical background in electrical engineering. At minimum, a Bachelor’s in EE is
required, and a Maser’s is preferred. - ≥8 years’ experience supporting or developing complex SoC/silicon products for Server, Storage, and/or
Networking applications. - Professional attitude with the ability to prioritize a dynamic list of multiple tasks, to plan and prepare for
customer meetings in advance, and to work with minimal guidance and supervision. - Entrepreneurial, open-mind behavior and can-do attitude. Think and act fast with the customer in mind!
- Authorized to work in Canada and start immediately.
Required Experience:
- Experience with integrating C/C++ in System Verilog environments using DPI/PLI
- Ability to use scripting tools (Perl/Python) to automate verification infrastructure.
- Experience in developing infrastructure and tests in a hybrid directed and constrained random
environments - Must be able to work independently to develop test-plans, and related test-sequences in UVM to
generate stimuli and work collaboratively with RTL designers to debug failures. - Develop user-controlled random constraints in transaction-based verification methodology. Experience
writing assertions, cover properties and analyzing coverage data - Must have prior experience using Verification IPs from 3rd party vendors for communication protocols
such as PCI-Express (Gen-3 and above), Ethernet, Infiniband, DDR, NVMe, USB, etc. - Develop VIP abstraction layers to simplify and scale verification deployments
Preferred Experience:
- S/W debugging for SoC based designs in the area of kernel/device-drivers/u-boot
- Physical Layer, Link Layer and Transaction Layer verification expertise in PCIe protocol.
- Experience in memory technologies like DDR4/DDR5/HBM.
- Experience with FPGA-based verification/emulation.
Base salary range is $165,000 CAD -$210,000 CAD, and will be determined based on the candidate's capabilities and employees in similar positions.
We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.
Skills Required
- Bachelor's degree in Electrical Engineering
- Master's degree in Electrical Engineering
- 8+ years supporting or developing complex SoC/silicon products for server, storage, or networking
- Authorized to work in Canada and able to start immediately
- Experience with UVM-based verification environments
- Experience integrating C/C++ with SystemVerilog environments using DPI/PLI
- Use of scripting tools (Perl, Python) to automate verification infrastructure
- Develop infrastructure and tests in hybrid directed and constrained-random environments
- Ability to develop test plans and UVM test sequences and debug failures with RTL designers
- Develop user-controlled random constraints, write assertions and cover properties, analyze coverage data
- Prior experience using 3rd-party Verification IPs for protocols (PCIe Gen3+, Ethernet, InfiniBand, DDR, NVMe, USB)
- Develop VIP abstraction layers to simplify and scale verification deployments
- Strong academic and technical background in electrical engineering
- Professional attitude, ability to prioritize multiple tasks and work with minimal supervision
- Entrepreneurial, open-minded, can-do attitude
- Software debugging for SoC (kernel/device-drivers/u-boot)
- Physical, Link, and Transaction Layer PCIe verification expertise
- Experience with memory technologies (DDR4, DDR5, HBM)
- Experience with FPGA-based verification/emulation
What We Do
Astera Labs Inc., a fabless semiconductor company headquartered in the heart of California’s Silicon Valley, is a leader in purpose-built connectivity solutions for data-centric systems throughout the data center. Partnering with leading processor vendors, cloud service providers, seasoned investors, and world-class manufacturing companies, Astera Labs is helping customers remove performance bottlenecks in data-intensive systems that are limiting the true potential of applications such as artificial intelligence and machine learning. The company’s product portfolio includes system-aware semiconductor integrated circuits, boards, and services to enable robust CXL, PCIe, and Ethernet connectivity.
