Principal Design Engineer

Posted 8 Hours Ago
Be an Early Applicant
Bangalore, Bengaluru Urban, Karnataka, IND
In-Office
Senior level
Artificial Intelligence • Cloud • Hardware • Software • Semiconductor
The Role
Lead design and development of high-speed memory IP (GDDR7/DDR5/LPDDR6). Perform analog design, layout, digital integration, documentation, silicon validation, and customer-facing discussions throughout full IP lifecycle from specification to silicon characterization.
Summary Generated by Built In
At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

Responsibilities :

B.Tech/BE/ME/Mtech 

Job Description

Design and lead high speed IP (GDDR7,DDR5,LPDDR6)  development. Need to be a strong individual contributor in analog domain. Will be required to participate in all aspects of development – analog design, layout, digital design, documentation, and silicon validation. Would be required to participate in customer facing discussions. 

Requirements

B.Tech/BE/ME/Mtech 

Exp - 5 +yrs

•                 Hands on design experience and leading GDDR/DDR/LPDDR IP’s

•                 Must have participated in full cycles of analog IP creation – right from spec to silicon debug and char

•                 Must have good communication skills and should be team player.

•                 Working experience in GDDR, DDR, LPDDR)  development is must

      

We’re doing work that matters. Help us solve what others can’t.

Skills Required

  • B.Tech/BE/ME/MTech degree
  • 5+ years experience
  • Hands-on design experience and leading GDDR/DDR/LPDDR IP development
  • Participation in full analog IP lifecycle from specification to silicon debug and characterization
  • Experience in analog design, layout, digital design, and silicon validation
  • Good communication skills and ability to work in a team; customer-facing capability

Cadence Design Systems Compensation & Benefits Highlights

The following summarizes recurring compensation and benefits themes identified from responses generated by popular LLMs to common candidate questions about Cadence Design Systems and has not been reviewed or approved by Cadence Design Systems.

  • Equity Value & Accessibility A discounted ESPP with a lookback feature and equity included in total compensation make ownership broadly accessible and potentially meaningful. Structured compensation at an industry leader adds predictability to equity participation.
  • Healthcare Strength Medical, dental, and vision coverage are described as solid, with mental‑health/EAP and fertility support enhancing the offering. The breadth across core care and family‑building needs strengthens the healthcare package.
  • Leave & Time Off Breadth Global Recharge Days, volunteer time off, and companywide breaks indicate a comprehensive time‑off framework. In addition, many salaried roles are described as having flexible or generous PTO policies.

Cadence Design Systems Insights

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The Company
HQ: San Jose, CA
8,216 Employees
Year Founded: 1988

What We Do

Cadence enables electronic systems and semiconductor companies to create the innovative end products that are transforming the way people live, work and play. Cadence® software, hardware and IP are used by customers to deliver products to market faster. The company's Intelligent System Design strategy helps customers develop differentiated products—from chips to boards to intelligent systems—in mobile, consumer, cloud, data center, automotive, aerospace, IoT, industrial and other market segments. Cadence is listed as one of Fortune Magazine's 100 Best Companies to Work For.

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