Design Verification expert with good subsystem and SOC level verification. Must possess excellent debug skills. Expert in developing SV UVM based testbenches. Ability to coach and mentor less experience teammates. Should have worked on time-bounded projects leading to Si realization.
Independently handle verification of complex modules or own significant piece in subsystem / SOC based verification. Define methodology for subsystem/SOC verification. Mentor less experienced engineers to bring them up as independent verification engineer. Follow systematic approach of metric driven verification with meticulous attention to quality and completeness. Should be able work closely across teams to meet delivery timelines.
Required experience
- Worked on Subsystem / SOC level verification projects
- Experience in ARM based designs.
- In-depth knowledge SV-UVM
- Expertise in architecting, design and development of scalable verification environments from scratch. Define verification architecture and verification strategy
- Expertise in verification test plan development, test cases coding; Execute and debug test cases to achieve functional and code coverage goals
- Experience in C based testcase development
- Strong knowledge of AMBA protocols like AXI, ACE, APB, AHB.
- Good knowledge of at least one of the USB/PCIE/Ethernet/DDR/LPDDR or similar protocols
- Strong problem solving skills. Exhibit discipline, thoroughness and methodical approach in solving problems
- Ability to work with stakeholders across cross-functional teams – Architecture, Design, Internal and External Customers
- Experience in mentoring junior engineers
- Self-driven and committed individual who can work in a fast paced project environment
Desirable skills and experience
- Prior experience with Cadence tools and flows is highly desirable
- Familiarity with ARM/CPU architectures is a plus
- Experience in developing c-based test cases for SOC verification
- Experience with assembly language programming
- Good knowledge of some of the protocols like UART, I2C, SPI, JTAG
- Embedded C code development and debug
- Formal Verification experience
- Cadence verification tool experience
Strong vocabulary, communication, organizational, planning, and presentation skills are essential. Ability to work independently and productively with high quality output and results in a fast paced and dynamic environment. A strong positive attitude and ability to work in a team is a must. Self-motivated and willing take up additional responsibilities to contribute to team’s success.
We’re doing work that matters. Help us solve what others can’t.Skills Required
- Experience in subsystem/SOC level verification projects
- In-depth knowledge of SV-UVM
- Expertise in verification test plan development
- Strong problem solving skills
- Experience in mentoring junior engineers
Cadence Design Systems Compensation & Benefits Highlights
The following summarizes recurring compensation and benefits themes identified from responses generated by popular LLMs to common candidate questions about Cadence Design Systems and has not been reviewed or approved by Cadence Design Systems.
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Equity Value & Accessibility — A discounted ESPP with a lookback feature and equity included in total compensation make ownership broadly accessible and potentially meaningful. Structured compensation at an industry leader adds predictability to equity participation.
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Healthcare Strength — Medical, dental, and vision coverage are described as solid, with mental‑health/EAP and fertility support enhancing the offering. The breadth across core care and family‑building needs strengthens the healthcare package.
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Leave & Time Off Breadth — Global Recharge Days, volunteer time off, and companywide breaks indicate a comprehensive time‑off framework. In addition, many salaried roles are described as having flexible or generous PTO policies.
Cadence Design Systems Insights
What We Do
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