Principal Design Engineer

Position Description:

• Design Verification role for IP development team.
• B. Tech/M.Tech with 8- 12 years of relevant experience.
• Position is based in Bangalore/Noida, part of Cadence IP Group.-> Preferred location is Bangalore.
• Verification role for Serial and Interface Design IPs verification (PCIe, CCIX, CXL, USB, Ethernet, SATA/SAS, UFS, SPI, HDMI, MIPI, I3C)
• UVM testbench development to build a robust, scalable and efficient testbench to verify the design IPs.
• In addition to UVM functional verification, role could involve Formal verification of complex design modules.
• In addition to UVM functional verification, role could involve participating in Emulation qualification of design IPs.
• Understand design and produce detailed verification strategy and test plan.
• Self-starter and learner with passion for getting the job done on time with great quality.
• Strong problem solving, analytical and debug skills
• Excellent verbal and written communications skills
• Clearly communicate project status, issues etc.

Behavioral skills required:

• Must possess strong written, verbal and presentation skills.
• Good communication and interpersonal skills, demonstrate teamwork and collaboration skills.
• Ability to establish a close working relationship with both customer peers and management.
• Explore what’s possible to get the job done, including creative use of unconventional solutions
• Work effectively across functions and geographies
• Push to raise the bar while always operating with integrity