Principal Design Engineer

Cadence is a pivotal leader in electronic design, building upon more than 30 years of computational software expertise. The company applies its underlying Intelligent System Design strategy to deliver software, hardware and IP that turn design concepts into reality.  Cadence customers are the world’s most innovative companies, delivering extraordinary electronic products from chips to boards to systems for the most dynamic market applications including consumer, hyperscale computing, 5G communications, automotive, aerospace industrial and health.

The Cadence Advantage

• The opportunity to work on cutting-edge technology in an environment that encourages you to be creative, innovative, and to make an impact.
• Cadence’s employee-friendly policies focus on the physical and mental well-being of employees, career development, providing opportunities for learning, and celebrating success in recognition of specific needs of the employees.
• The unique “One Cadence – One Team” culture promotes collaboration within and across teams to ensure customer success
• Multiple avenues of learning and development available for employees to explore as per their specific requirement and interests
• You get to work with a diverse team of passionate, dedicated, and talented individuals who go above and beyond for our customers, our communities, and each other—every day.

for the post of "Design Engineering Manager (IP System Validation)"

BE/BTECH/ME/MTECH Or Equivalent Degree

Exp:8-14years

What we do :

•            Develop and perform System Validation of PCIe/CXL/UCIe IP's from Cadence against the standard specification and Market expectations.

•            Silicon bring up, PCIe/CXL/UCIe Link Level testing, working with standard group for Compliance (PCI-SIG/CXL Consortium)

•            Design experiments to root cause PHY/Link Level issues and lead debug/resolution efforts in collaboration with Design/Verification teams.

•            Firmware Development for our High Speed Serdes like PCIe, CXL , UCIe ,ethernet.

•            Application boards and Subsystem Design along with test suites for in-house testing and Customer Demo

•            Engage in PCIe/CXL interop’s with the latest Motherboards (x86/AMD/Intel) and lead Customer debugs.

Required/Preferred Experience:

BE/BTECH/ME/MTECH Or Equivalent Degree

Exp:8-14years

•            Hands on thorough knowledge of high speed protocols like PCIe/CXL/UCIe

•            Working knowledge of SerDes Architecture, TX/RX equalization, PLL/CDR and SerDes PCS Layer. Experience on PAM4 (32G+) SerDes is a bonus.

•            Strong background in developing automation techniques for execution efficiency, data analysis and reporting.

•            History of taking PCIe/CXL products to Compliance.

•            8-14 years (with Btech) or 8 years (with Mtech) experience in Post-Silicon PHY, PCIe/CXL Interoperablity and Link Level Testing.

•            Knowledge of Schematics Capture and PCB Layout tools to go through and debug application boards.

•            2-3 years of management experience leading/mentoring a small team of engineers 

•            Debug skills and Experience in using lab equipment such as Oscilloscopes, Bit Error Rate Testers, Protocol Exercisers, Analyzers