Principal Design Engineer

Posted 6 Hours Ago
Be an Early Applicant
Pune, Mahārāshtra
Senior level
Cloud • Hardware • Software • Semiconductor
The Role
The Principal Design Engineer at Cadence will develop performance models for DDR memory controllers, analyze architectural trade-offs, and create automated scripts for performance metric generation. This role requires strong coding skills in C++ and SystemC, along with a solid foundation in computer architecture and hardware modeling.
Summary Generated by Built In

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

Performance Modeling Engineer

Location – India (Pune)

Summary

We are looking for modeling engineers to help develop performance models, perform architectural tradeoff analysis, and enable data driven design decisions for our next generation DDR memory controller architectures that can meet today’s complex SoC and workload requirements. Hardware modelling experience (C++/SystemC/TLM/Python) and computer architecture foundation is desired.

Responsibilities

  • Develop cycle-level performance models in SystemC or C++
  • Correlate performance models to match RTL configurations and traffic conditions
  • Work with Memory Architects to understand feature requirements, architectural specifications and implement in the model
  • Analyze architectural trade-offs (throughput, hardware cost) across different scenarios and architectural choices
  • Develop synthetic memory traffic/traces that are representative of real-world applications (CPU, GPU, DSP, NoC, etc)
  • Develop scripts to automate generation of various performance metrics and statistics post RTL simulation that helps identify performance bottlenecks

Required Skills

  • BE/B.Tech ME/M.Tech in ECE, E&TC, CS or similar
  • 8+ years of experience in hardware modeling, functional or performance
  • Strong coding skills in C++, SystemC and Transaction Level Modeling (TLM)
  • Basic understanding of performance principles, Queuing Theory, throughput/latency tradeoffs

Additional Skills

  • Understand RTL-Verilog, SV, UVM and experience analyzing waveforms
  • Understand memory protocols and timing – DDR4, DDR5, LP4, LP5
  • Experience using performance simulators – Memory Controller, NoC, CPU models
  • Coding in Python and familiarity with packages like Pandas, Matplotlib
  • Experience working with performance benchmarks – SPEC, STREAM, etc
  • Concepts related to Quality of Service (QoS) and how memory controller can tradeoff performance and latencies

We’re doing work that matters. Help us solve what others can’t.

Top Skills

C++
Python
Systemc
The Company
HQ: San Jose, CA
8,216 Employees
On-site Workplace
Year Founded: 1988

What We Do

Cadence enables electronic systems and semiconductor companies to create the innovative end products that are transforming the way people live, work and play. Cadence® software, hardware and IP are used by customers to deliver products to market faster. The company's Intelligent System Design strategy helps customers develop differentiated products—from chips to boards to intelligent systems—in mobile, consumer, cloud, data center, automotive, aerospace, IoT, industrial and other market segments. Cadence is listed as one of Fortune Magazine's 100 Best Companies to Work For.

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