Principal Design Engineer

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Job Description:

We are seeking a highly skilled Principal Design Engineer to lead and support the development of digital IP modules for advanced 32-bit microcontroller and microprocessor product families.

Job Responsibilities:

• Design IP modules for 32-bit microprocessors and microcontrollers products
• Guide and support the IP development of various modules by different team members
• Plan, track and maintain IP development project timelines and quality metrics
• Collaborate with cross functional teams to meet business unit objectives such as Applications, Marketing, Analog, CAD and other design organizations
• Work with Architecture teams to review IP specifications and objectives. Provide feedback on design feasibility and implementation complexity
• Generate and maintain Micro Architecture Specification (MAS) at module level and other design flow documentation
• Work with Verification team to debug and fix issues found in simulation
• Support the integration of IP modules into SoC products. Provide support for IP related SoC level Verification, Emulation, Silicon debug and ECOs
• Partner with Architecture teams to evaluate IP from external vendors. Liaise with vendors to bring IP in-house for use on SoC products
• Define, develop, improve design process flows and methodologies for continuous improvement
• Work with synthesis/STA engineers to investigate timing concerns at module and SoC level and provide appropriate constraints for use by the BackEnd team
• Work with DFT engineers to improve test coverage of IP modules
• Validate and debug silicon products in support of Release to Production

Requirements/Qualifications:

• Ability to technically lead and supervise/mentor a team of 2-3 design engineers
• Must have leadership, mentoring and project management skills to drive and support IP development team
• Excellent communication skills. Comfortable presenting in technical forums
• Must be able to write reusable System Verilog RTL code, follow design guidelines and best practices
• Able to write good documentation for micro-architecture specification (MAS) and design flows/methodologies
• Able to provide constraints for synthesis and static timing analysis
• Able to run design quality checks such as Lint, CDC, formal equivalency, power estimation
• Strong scripting and automation skills
• Strong analytical, and problem solving skills, as well as hands-on debugging skills
• Knowledge of AXI/AHB interfaces/protocols required
• Experience with low power design techniques highly desirable
• Understanding of Flash / non-volatile memory-based architectures a plus
• Understanding of communication protocols such as Ethernet/1588, USB 2/3, I3C, CAN-FD, and MIPI desirable
• Familiarity with System Verilog for verification, UVM, assertion-based verification is desirable
• Experience in analog and mixed signal design a plus (e.g. ADC)
• Knowledge of audio protocols a plus (e.g. SPDIF, I2S, DSD, TDM)
• Experience with Git, Bitbucket, JIRA, and MS Project a plus
• Must be able to function in a fast-paced engineering environment that is simultaneously responsible for new IP design and addressing bugs/weaknesses in existing solutions
• Must be a team player. Must be able to work effectively with a global team
• Must be able to communicate well
• Master’s degree in a relevant engineering discipline with 7+ years or Bachelor’s with 10+ years of industry experience

Travel Time:

0% - 25%

Physical Attributes:

Hearing, Seeing, Talking

Physical Requirements:

80% sitting, 10% walking, 10% standing

Microchip Technology Inc is an equal opportunity/affirmative action employer. All qualified applicants will receive consideration for employment without regard to sex, gender identity, sexual orientation, race, color, religion, national origin, disability, protected Veteran status, age, or any other characteristic protected by law.
For more information on applicable equal employment regulations, please refer to the EEO is the Law Poster and the EEO is the Law Poster Supplement. Please also refer to the Pay Transparency Policy Statement.