Principal ASIC Design Verification Engineer

Posted Yesterday
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Santa Clara, CA, USA
In-Office
138K-318K Annually
Expert/Leader
Artificial Intelligence • Information Technology • Software • Consulting
The Role
Lead development and maintenance of SystemVerilog/UVM verification environments for high-performance SoCs. Create test plans, execute constrained-random tests, drive coverage closure, debug issues, automate flows with Python/Perl, run unit and regression tests, and collaborate with design teams.
Summary Generated by Built In
Bright Vision Technologies is a forward-thinking software development company dedicated to building innovative solutions that help businesses automate and optimize their operations. We leverage cutting-edge technologies to create scalable, secure, and user-friendly applications.
As we continue to grow, we’re looking for a skilled Principal Design Verification Engineer – UAL & PCIe Subsystems to join our dynamic team and contribute to our mission of transforming business processes through technology.
This is a fantastic opportunity to join an established and well-respected organization offering tremendous career growth potential.
Job Title: Principal Design Verification Engineer – UAL & PCIe Subsystems
Location: Santa Clara, CA (Onsite)
Salary: $138,000 – $317,800
Bonus + RSUs
Job Summary
We are looking for an experienced Principal Design Verification Engineer to support verification of high-performance SoC designs. The ideal candidate will have strong expertise in SystemVerilog, UVM, and verification methodologies, along with experience in UAL or PCIe protocols.
Responsibilities
  • Develop and maintain verification environments using SystemVerilog and UVM.
  • Create verification test plans and drive coverage closure.
  • Develop and execute test cases for SoC verification.
  • Debug design and verification issues.
  • Develop automation tools using Python or Perl.
  • Perform unit and regression testing.
  • Collaborate with design and engineering teams throughout the development cycle.
Required Skills
  • BS/MS/PhD in Computer Science, Electrical Engineering, or Computer Engineering.
  • 10–12 years of Design Verification experience.
  • Strong experience with SystemVerilog and UVM.
  • Experience creating verification plans and constrained-random test environments.
  • Python or Perl scripting experience.
  • Experience with EDA verification tools.
  • Strong Linux and Object-Oriented Programming knowledge.
  • Good programming skills in C++.
  • Working knowledge of UAL or PCIe protocols.
Relocation Assistance Available
Visa Sponsorship Available

Would you like to know more about this opportunity? For immediate consideration, please send your resume to [email protected] or contact us at (908) 650-6382
Bright Vision Technologies, we are committed to equal employment opportunities and fostering an inclusive work environment. If you require accommodations during the recruitment process, please let us know.
Position offered by “No Fee agency.”
 

Skills Required

  • BS/MS/PhD in Computer Science, Electrical Engineering, or Computer Engineering
  • 10-12 years of Design Verification experience
  • Strong experience with SystemVerilog
  • Strong experience with UVM
  • Experience creating verification plans and constrained-random test environments
  • Python or Perl scripting experience
  • Experience with EDA verification tools
  • Strong Linux knowledge
  • Object-Oriented Programming knowledge
  • Good programming skills in C++
  • Working knowledge of UAL or PCIe protocols
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The Company
53 Employees
Year Founded: 2020

What We Do

Bright Vision Technologies is a minority-owned organization founded in July 2020 and based in New Jersey, USA. The company specializes in delivering top-tier staffing and IT consulting services, including custom computer programming and systems design. Additionally, they are a product engineering firm with a flagship AI-powered talent intelligence and enterprise automation platform called Lumina, which helps transform IT into a strategic asset for their valued partners.

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