Principal ASIC Design Engineer

About Marvell

Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities. 

At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead. 

This is an existing vacancy.

Your Team, Your Impact

As a Digital IC Design, Principal Engineer at Marvell, you will be part of the Central Engineering organization—the core hub of innovation that supports all business units across the company. If Marvell were a wheel, Central Engineering would be the central hub, delivering foundational IP leveraged by teams spanning Automotive, Storage, Security, and Networking.
You will join a small, high-impact digital design team where your contributions directly influence multiple product lines and strategic initiatives. The team is composed of some of the industry’s strongest problem solvers, tackling complex silicon challenges that shape Marvell’s technology roadmap.
In addition to supporting internal business units, this team collaborates with leading semiconductor companies and major global technology firms—organizations that are widely recognized and respected across the industry.

What You Can Expect

As a Principal Design Engineer, you will lead the development and deployment of design flows and methodologies that bridge front-end design and back-end physical implementation. You will work cross-functionally with Architecture, RTL Design, Physical Design, Timing, and DFT teams to drive seamless integration throughout the SoC development lifecycle.
In this role, you will establish and drive EDA methodologies for front-end design, enabling early visibility into back-end physical design challenges while ensuring that design intent is accurately reflected through robust constraints and implementation strategies.
Key Responsibilities include, but are not limited to:
•    Define and implement front-end methodologies for early-stage synthesis, static timing analysis, and clock/reset domain crossing (CDC/RDC).
•    Develop and optimize flows that enable early detection of physical design and timing challenges, ensuring efficient handoff to back-end teams.
•    Collaborate closely with physical design teams to provide high-quality constraints aligned with architectural and design intent.
•    Drive the delivery of complex, high-performance, timing-critical designs across all phases of the SoC front-end design flow, including timing closure and power optimization.

What We're Looking For

· Bachelor’s degree in computer science, Electrical Engineering, or a related field with 10–20 years of relevant industry experience; or a Master’s/PhD in a related field with 8–20 years of experience.

· Strong foundation in ASIC design, verification, architecture, and front-end design methodologies.

· Solid understanding of ASIC back-end design, EDA tools, and associated design methodologies.

· Hands-on experience with SoC architecture, including processor cores, memory subsystems, and peripheral interfaces.

· Extensive experience with Verilog/SystemVerilog, including linting, synthesis, static timing analysis, clock and reset domain crossing (CDC/RDC), and formal equivalence checking between RTL and gate-level netlists.

· Proficiency in scripting and automation using languages such as Python or Perl.

· Demonstrated track record of delivering production-quality silicon on aggressive development timelines.

· Experience with high-speed protocol domains such as Ethernet, PCIe, and emerging standards (e.g., UALink) is a plus.

· Familiarity with applying AI/ML techniques to ASIC development is a plus.

· Experience designing, verifying, and testing high-speed datapath logic is a plus.

· Expertise working with large datapath FPGAs and advanced ASIC technology nodes is desirable.

Expected Base Pay Range (CAD)

145,800 - 194,400, $ per annum

Additional Compensation and Benefit Elements

With competitive compensation and great benefits, you will enjoy our workstyle within an environment of shared collaboration, transparency, and inclusivity. We’re dedicated to giving our people the tools and resources they need to succeed in doing work that matters, and to grow and develop with us. For additional information on what it’s like to work at Marvell, visit our Careers page.

All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.

Interview Integrity 

To support fair and authentic hiring practices, candidates are not permitted to use AI tools (such as transcription apps, real-time answer generators like ChatGPT or Copilot, or automated note-taking bots) during interviews.

These tools must not be used to record, assist with, or enhance responses in any way. Our interviews are designed to evaluate your individual experience, thought process, and communication skills in real time. Use of AI tools without prior instruction from the interviewer will result in disqualification from the hiring process.

This position may require access to technology and/or software subject to U.S. export control laws and regulations, including the Export Administration Regulations (EAR). As such, applicants must be eligible to access export-controlled information as defined under applicable law. Marvell may be required to obtain export licensing approval from the U.S. Department of Commerce and/or the U.S. Department of State. Except for U.S. citizens, lawful permanent residents, or protected individuals as defined by 8 U.S.C. 1324b(a)(3), all applicants may be subject to an export license review process prior to employment.

Marvell may employ artificial intelligence technologies to assist in the evaluation of job applications. All application reviews include meaningful human involvement, and no hiring decisions are made solely on the basis of automated processing.

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