Principal Application Engineer - Design Verification

Job Responsibility:

1. Work closely with the Sales team to identify and scope opportunities for Cadence SoC Verification solution, simulation Emulation and Acceleration products.

2. Plan, execute and manage key technical evaluations and benchmark with existing and potential customers.

3. Train, ramp-up and accompany customer project.

4. Conduct basic and advanced trainings, presentations and demos as necessary.

5. Providing technical expertise to address clients’ queries, which need expert involvement.

6. Aligned closely with corporate engineering and sales/marketing team on customer requirement for product direction/improvement.

Job Requirements:

4-6 or above years’ experience in the following areas:

1. Design experience in Verilog/VHDL for IP or SoC chip level.

2. Verification with knowledge of System Verilog/VHDL and HDL simulators.

3. Experience of using formal verification, JasperGold experience is a plus.

4. Advanced Verification Methodology like UVM is a plus.

5. Strong verbal and written communication skills in Japanese is needed.

6. Business-level English proficiency is preferred.

7. Strong teamwork skills with good human relationship.