PRINCIPAL ANALOG MIXED SIGNAL ENGINEER

Posted 22 Days Ago
Be an Early Applicant
3 Locations
In-Office or Remote
2M-2M Annually
Expert/Leader
Edtech • HR Tech • Information Technology • Professional Services
The Role
Lead end-to-end analog and mixed-signal ASIC/SoC IP development, including architecture, circuit design, verification, sign-off, tape-out, silicon bring-up, characterization, yield improvement, and production support. Define technical strategy, lead design reviews, mentor engineering teams, collaborate with digital, physical design, verification, packaging, and test groups, and engage customers on technical requirements and solutions.
Summary Generated by Built In

 HIRING | PRINCIPAL ANALOG MIXED SIGNAL ENGINEER 


 Location: Trivandrum | Bangalore | Chennai
 Experience: 12–18 Years
 CTC: Up to ₹19 LPA
 Work Mode: Work From Office (WFO)
 ROLE OVERVIEW

We are looking for an experienced Principal Analog Mixed Signal Engineer to lead end-to-end ASIC/SoC Analog & Mixed-Signal IP development, from architecture and circuit design to tape-out, silicon bring-up, characterization and production support.

 KEY RESPONSIBILITIES


• Own AMS IP/subsystem development from concept to production
• Define architecture, roadmap and technical strategy
• Lead design reviews and mentor AMS teams
• Drive verification, sign-off, tape-out and silicon validation
• Support characterization, yield improvement and productization
• Collaborate with Digital, Physical Design, Verification, Packaging & Test teams
• Interface with customers on technical requirements and solutions? MUST-HAVE SKILLS
• PLL/DLL, ADC/DAC, Bandgap, LDO & Power Management
• Oscillators, Comparators, Charge Pumps & Sensor Interfaces
• Cadence Virtuoso, Spectre/APS, ADE XL/Explorer/Assembler
• HSPICE & AMS Verification
• Verilog-A / Verilog-AMS
• PVT, Monte Carlo, mismatch, noise & reliability analysis
• DRC, LVS, ERC, PEX & post-layout simulation
• Multiple successful silicon tape-outs
• Silicon bring-up & characterization experience
 PREFERRED SKILLS


• FinFET technology exposure
• SerDes experience
• MIPI experience
• USB experience
• PCIe experience
• DDR PHY experience
• ISO 26262 / IEC 61508 exposure
• Low-power analog design techniques
• Python / Perl / TCL scripting
• Productization & yield improvement experience

 Qualification: B.E./B.Tech/M.E./M.Tech in Electronics, Electrical, VLSI, Microelectronics or related field.




Skills Required

  • 12–18 years of relevant experience
  • Experience developing analog and mixed-signal ASIC/SoC IP from architecture through production
  • Expertise with PLL/DLL, ADC/DAC, bandgap, LDO, and power management circuits
  • Experience with oscillators, comparators, charge pumps, and sensor interfaces
  • Proficiency with Cadence Virtuoso, Spectre/APS, and ADE XL/Explorer/Assembler
  • Experience with HSPICE and AMS verification
  • Proficiency in Verilog-A and Verilog-AMS
  • Experience with PVT, Monte Carlo, mismatch, noise, and reliability analysis
  • Experience with DRC, LVS, ERC, PEX, and post-layout simulation
  • Multiple successful silicon tape-outs
  • Silicon bring-up and characterization experience
  • B.E., B.Tech, M.E., or M.Tech in Electronics, Electrical, VLSI, Microelectronics, or a related field
  • FinFET technology exposure
  • SerDes experience
  • MIPI experience
  • USB experience
  • PCIe experience
  • DDR PHY experience
  • ISO 26262 or IEC 61508 exposure
  • Low-power analog design experience
  • Python, Perl, or TCL scripting
  • Productization and yield improvement experience
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The Company
10 Employees
Year Founded: 2018

What We Do

Vrinda International is a Chandigarh-based recruitment and education consultancy connecting job seekers and employers through domestic and international IT and non-IT hiring. It also supports students with overseas university admissions, visa applications, education guidance, and test preparation for IELTS, PTE, and other programs. Its tech-enabled talent portal provides job matching and career pathways across India and global markets, alongside staffing partnerships.

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