Pre-Silicon Verification Engineer

Job Details:

Job Description: 

Develops pre silicon functional validation tests to verify system will meet design requirements Creates test plans for RTL validation defining and running system simulation models and finding and implementing corrective measures for failing RTL tests Analyzes and uses results to modify testing
Knowledge of Verilog ,System Verilog, UVM Based Testbench development
Understanding of code functional coverage system Verilog assertion coding
General Scripting and programming skills Python Per TCL etc
Formal verification would be a plus
IP Level testbench development using SV and UVM
Testplan development using Verification planner, tracking and closer of code and functional coverage
Req Location: SRR4 Bangalore
Job Description
Your responsibilities include but are not limited to:

• Define and develop test env to verify the IP/Sub System functionality.
• Define Test plans and develop Tests contents.Define Checkers/monitors strategy.
• Define and Develop Assertions.Define Cover points and analyze functional coverage with analysis.
• Define Volume regressions strategy and run simulations followed by failure debugs.
• Develop formal verification assertions, properties.
• Define and perform Performance Verification.
• Mentoring and coaching junior verification engineers.
• Leadership to manage stake holders with end to end objectives in mind.

The candidate should have ability to work effectively with both internal and external teams/stakeholders. Should possess strong problem solving/communication skills. Should be a very good team player.

Qualifications:Qualifications
You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.
Minimum Qualifications:
Candidate should possess a Bachelor's degree in Electrical, Electronics, Computer Engineering or Computer Science or any related field with 7+ years' experience -OR - a Master's degree Electrical, Electronics, Computer Engineering or Computer Science or any related field with 5+ years experience -OR- PhD degree in Electrical, Electronics, Computer Engineering or Computer Science or any related field with 3+ years experience in:
VLSI design.
Verification/validation tests.
Expertise in System Verilog/C++/OVM or UVM methodology and/or Formal Verification techniques.
Preferred qualification:
System simulation models, and debugging RTL/tests.
Experience with Cache Coherency protocols or PCIE/CXL would be a huge plus

Job Type:Experienced Hire

Shift:Shift 1 (India)

Primary Location: India, Bangalore

Additional Locations:

Business group:In the Design Engineering Group (DEG), we take pride in developing the best-in-class SOCs, Cores, and IPs that power Intel’s products. From development, to integration, validation, and manufacturing readiness, our mission is to deliver leadership products through the pursuit of Moore’s Law and groundbreaking innovations.  DEG is Intel’s engineering group, supplying silicon to business units as well as other engineering teams.  As a critical provider of all Intel products, DEG leadership has a responsibility to ensure the delivery of these products in a cost efficient and effective manner.

Posting Statement:All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.Position of TrustN/A

Work Model for this Role

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.