Evaluate the PPA of our design as part of the chip architecture planning process.
Perform synthesis, logic equivalence checking, SDC & UPF development, and static timing analysis.
Work collaboratively with a design house to achieve the best outcome.
Bachelor’s degree in Electronic Engineering or other technically related fields
Experience with using Verilog HDL for digital logic design
2+ years of industry experience with logic synthesis, LEC, STA, producing SDC & UPF
Experience with EDA tools (Synopsys tool chain, DC, FM, PT) and scripting (TCL, shell)
5+ years of industry experience with ASIC design
DFT, Place and Route experience
Experience with high-speed connectivity IPs (e.g., PCIe, Ethernet, HBM)
Top Skills
What We Do
FuriosaAI designs and develops data center accelerators for the most advanced AI models and applications.
Our mission is to make AI computing sustainable so everyone on Earth has access to powerful AI.
Our Background
Three misfit engineers with each from HW, SW and algorithm fields who had previously worked for AMD, Qualcomm and Samsung got together and founded FuriosaAI in 2017 to build the world’s best AI chips.
The company has raised more than $100 million, with investments from DSC Investment, Korea Development Bank, and Naver, the largest internet provider in Korea. We have partnered on our first two products with a wide range of industry leaders including TSMC, ASUS, SK Hynix, GUC, and Samsung. FuriosaAI now has over 140 employees across Seoul, Silicon Valley, and Europe.
Our Approach
We are building full stack solutions to offer the most optimal combination of programmability, efficiency, and ease of use. We achieve this through a “first principles” approach to engineering: We start with the core problem, which is how to accelerate.
