Physical Design Staff Engineer

Reposted 7 Days Ago
Be an Early Applicant
Bangalore, Bengaluru Urban, Karnataka
In-Office
Senior level
Semiconductor
We create custom semiconductor solutions that move, process, store, and secure data quickly and reliably.
The Role
The role involves physical design and methodology for high-performance processor chips, performing synthesis, place and route, and timing analysis, while collaborating with the RTL design team to address issues.
Summary Generated by Built In

About Marvell

Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, automotive, and carrier architectures, our innovative technology is enabling new possibilities. 

At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead. 

Your Team, Your Impact

Built on decades of expertise and execution, Marvell’s custom Processor/ASIC solution offers a differentiated approach with a best-in-class portfolio of data infrastructure intellectual property (IP) and a wide array of flexible business models. In this unique role, you’ll have the opportunity to work on both the physical design and methodology for future designs of our next-generation, high-performance processor chips in a leading-edge CMOS process technology, targeted at server, 5G/6G, automotive, and networking applications.

What You Can Expect

  • Work with a global team on the physical design of complex chips as well as on developing methodologies to ensure an efficient and robust design process. Maintain, enhance, and support Marvell’s Place and Route Flow by leveraging industry-standard EDA tools.

  • Perform synthesis, place and route, and timing analysis and closure on multiple intermediate and complex logic blocks.

  • Develop and implement timing and logic ECOs, collaborating closely with the RTL design team to drive modifications that address congestion and timing issues.

  • Collaborate with the global timing team to debug and resolve block-level timing issues encountered at the partition level.

  • Engage with diverse engineering challenges within a collaborative and innovative environment at Marvell.

What We're Looking For

  • Have completed a Bachelor’s Degree in Electrical/Computer Engineering or related fields and have 6+ years of related professional experience OR a Master’s degree and/or PhD in Electrical/Computer Engineering, or related fields.

  • In your coursework, you must have completed a digital logic course and projects that involved circuit design, testing, and timing analysis.

  • Exposure and worked on Physical design projects on latest nodes.

  • Good understanding of standard RTL to GDS flows and methodology

  • Good scripting skills in languages such as Perl, tcl, and Python

  • Good object-oriented programming skills

  • Good understanding of digital logic and computer architecture

  • Knowledge of Verilog/VHDL

  • Good communication skills and self-discipline contributing in a team environment.

  • #LI-MN1

Additional Compensation and Benefit Elements

With competitive compensation and great benefits, you will enjoy our workstyle within an environment of shared collaboration, transparency, and inclusivity. We’re dedicated to giving our people the tools and resources they need to succeed in doing work that matters, and to grow and develop with us. For additional information on what it’s like to work at Marvell, visit our Careers page.

All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.

Interview Integrity
 

As part of our commitment to fair and authentic hiring practices, we ask that candidates do not use AI tools (e.g., transcription apps, real-time answer generators like ChatGPT, CoPilot, or note-taking bots) during interviews.
 
Our interviews are designed to assess your personal experience, thought process, and communication skills in real-time. If a candidate uses such tools during an interview, they will be disqualified from the hiring process.

This position may require access to technology and/or software subject to U.S. export control laws and regulations, including the Export Administration Regulations (EAR). As such, applicants must be eligible to access export-controlled information as defined under applicable law. Marvell may be required to obtain export licensing approval from the U.S. Department of Commerce and/or the U.S. Department of State. Except for U.S. citizens, lawful permanent residents, or protected individuals as defined by 8 U.S.C. 1324b(a)(3), all applicants may be subject to an export license review process prior to employment.

#LI-MN1

Top Skills

Eda Tools
Perl
Python
Tcl
Verilog
Vhdl
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The Company
HQ: Santa Clara, CA
6,500 Employees
Year Founded: 1995

What We Do

Marvell specializes in semiconductor solutions that power a wide range of industries, from data centers and 5G networks to AI, automotive, and storage applications. Our cutting-edge products are designed to meet the constantly evolving demands of a connected world, enabling faster, more efficient and more secure data processing and communication. With a focus on excellence and a commitment to advancing technology, we develop solutions that drive progress and transform industries.

Why Work With Us

Life at Marvell means being a part of new innovation and enduring technology; but it's also much more. Our diverse community is strengthened through cultural events, corporate gatherings and team-building activities, fostering collaboration and making work enjoyable. At Marvell, it's not just a job; it's an enriching, community-driven experience.

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