Physical Design engineers

𝗧𝗵𝗶𝘀 𝗿𝗼𝗹𝗲 𝗶𝘀 𝗳𝗼𝗿 𝗼𝗻𝗲 𝗼𝗳 𝘁𝗵𝗲 𝗪𝗲𝗲𝗸𝗱𝗮𝘆'𝘀 𝗰𝗹𝗶𝗲𝗻𝘁𝘀

𝗦𝗮𝗹𝗮𝗿𝘆 𝗿𝗮𝗻𝗴𝗲: 𝗥𝘀 𝟭𝟲𝟬𝟬𝟬𝟬𝟬 - 𝗥𝘀 𝟱𝟬𝟬𝟬𝟬𝟬𝟬 (𝗶𝗲 𝗜𝗡𝗥 𝟭𝟲-𝟱𝟬 𝗟𝗣𝗔)

Experience: 4+ yrs

Location: Bengaluru

Job Type: Full-time

We are seeking talented Physical Design Engineers to contribute to the implementation of high-performance ASIC and SoC designs across advanced semiconductor technology nodes. This role is ideal for professionals with strong expertise in Cadence physical design tools and Floorplanning, along with a passion for delivering optimized silicon solutions that meet aggressive power, performance, and area (PPA) goals.

As a Physical Design Engineer, you will work closely with RTL, Design Verification, DFT, STA, and Foundry teams throughout the complete physical implementation cycle. You will be responsible for developing efficient floorplans, driving timing closure, resolving implementation challenges, and ensuring successful tape-outs. This position offers the opportunity to work on cutting-edge semiconductor products while contributing to advanced implementation methodologies and continuous process improvements.

• Execute end-to-end physical design implementation from synthesized netlist through GDSII for ASIC and SoC projects.
• Develop and optimize floorplanning strategies to achieve target PPA while minimizing congestion and improving routability.
• Perform placement, clock tree synthesis (CTS), routing, timing optimization, and physical verification using Cadence implementation tools.
• Collaborate with RTL, DFT, STA, and Verification teams to resolve design issues and support successful physical implementation.
• Drive timing closure by resolving setup, hold, signal integrity, IR drop, electromigration, and congestion-related challenges.
• Support engineering change orders (ECOs), implementation updates, and design optimization throughout the project lifecycle.
• Perform design quality checks, physical verification, and signoff activities to ensure compliance with foundry and manufacturing requirements.
• Develop automation scripts to improve physical design productivity, reporting, and implementation efficiency.
• Participate in technical design reviews, identify implementation risks, and recommend improvements for better design quality and execution.
• Document implementation methodologies, design flows, and best practices while contributing to continuous process improvement initiatives.

• 4+ years of experience in Physical Design for ASIC or SoC implementation.
• Strong hands-on expertise with Cadence physical design tools, including Innovus and associated implementation solutions.
• Solid understanding of Floorplanning, placement, CTS, routing, timing closure, and physical signoff methodologies.
• Experience working with advanced semiconductor technology nodes and optimizing designs for power, performance, and area (PPA).
• Good understanding of static timing analysis, signal integrity, IR drop, electromigration, DRC, LVS, and physical verification flows.
• Familiarity with scripting languages such as TCL, Python, Perl, or Shell for automation and design flow optimization.
• Strong analytical, debugging, and problem-solving skills with the ability to resolve complex implementation challenges.
• Excellent collaboration and communication skills with experience working across multidisciplinary semiconductor engineering teams.
• Bachelor's or Master's degree in Electronics, Electrical Engineering, VLSI, Computer Engineering, or a related discipline.
• Passion for semiconductor innovation, continuous learning, and delivering high-quality silicon solutions within challenging project timelines.