Position: Physical Designer Engineer
Level: Mid- Senior
Location: West Bank-Onsite
Contract Type: Full-Time for 1-Year (Renewable)
Working hours: Palestine Time Zone
Salary: Competitive Package based on Experience
No. of Vacancies: 2
OverviewGGateway is seeking experienced Physical Design Engineers to join our team in supporting one of our international semiconductor clients. Engineers will work onsite from our West Bank office as part of a high-performance Physical Design team responsible for implementing complex SoCs from floorplanning through signoff. The ideal candidate has a strong ownership mindset, excellent debugging skills, and experience driving timing, power, area, and physical convergence on advanced technology nodes.
Responsibilities, Duties, and Expectations- Own and execute block- or chip-level physical implementation using Cadence Innovus.
- Drive floorplanning, power planning, placement, CTS, routing, ECO implementation, and physical convergence.
- Achieve timing closure across MCMM scenarios while optimizing PPA (Power, Performance, Area).
- Perform STA using PrimeTime/PrimeClosure and resolve setup, hold, SI, noise, and clock-related violations.
- Analyze and resolve congestion, short/open, DRC, LVS, antenna, IR-drop, EM, and physical signoff issues using industry-standard signoff tools (Calibre, ICV, Voltus, RedHawk…etc).
- Develop TCL, Python, Perl, or Shell scripts to automate implementation, reporting, and design checks.
- Collaborate closely with different teams throughout the implementation cycle.
- Participate in design reviews, root-cause analysis, methodology improvements, and best-practice development.
- For Senior Engineers: provide technical leadership, mentor junior engineers, review implementation strategies, and drive project execution to successful tape-out.
- Bachelor's degree in Electrical Engineering, Computer Engineering, or a related discipline.
- 5+ years of industry experience in digital physical design.
- Proven experience delivering successful tape-outs for complex SoCs at advanced technology nodes (5nm and below).
- Strong expertise in floorplanning, power planning, placement, CTS, routing, timing closure, ECOs, and signoff.
- Hands-on experience with Innovus, PrimeTime, and verification tools such as Calibre.
- Strong understanding of MCMM methodology, SI, IR-drop, EM, and low-power implementation.
- Excellent scripting skills in TCL plus Python, Perl, or Shell.
- Ability to lead technical discussions, mentor engineers, estimate schedules, and drive implementation independently.
- Bachelor's degree in Electrical Engineering, Computer Engineering, or a related discipline.
- 2–5 years of industry experience in digital physical design.
- Hands-on experience with floorplanning, placement, CTS, routing, timing closure, and physical verification.
- Hands-on experience with Innovus, PrimeTime, and verification tools such as Calibre.
- Experience with TCL scripting; Python or Perl.
- Strong analytical, debugging, communication, and teamwork skills.
- Experience with advanced technology nodes (7nm/5nm/3nm).
- Knowledge of UPF/CPF low-power implementation.
- Familiarity with Verilog/SystemVerilog and DFT concepts.
- Experience with CI/CD, regression automation, and design methodology development.
Skills Required
- Hands-on experience with Cadence Innovus
- Static timing analysis using PrimeTime and PrimeClosure
- Physical verification and signoff tools such as Calibre and ICV
- Power and reliability signoff tools such as Voltus and RedHawk
- Floorplanning, power planning, placement, CTS, routing, ECO implementation, and timing closure
- Develop TCL scripts and scripting in Python, Perl, or Shell
- Experience delivering tape-outs for complex SoCs at advanced nodes (senior candidates: 5nm and below)
- Knowledge of MCMM methodology, signal integrity, IR-drop, EM, and low-power implementation
- 2-5 years of industry experience in digital physical design (mid-level) or 5+ years for senior roles
- Bachelor's degree in Electrical Engineering, Computer Engineering, or related discipline
- Familiarity with Verilog/SystemVerilog and DFT concepts
- Experience with CI/CD, regression automation, and design methodology development
- Experience with advanced technology nodes (7nm/5nm/3nm)
What We Do
GGateway is a MENA based Software and R&D outsourcing services company. We not only provide the best technical skillsets to our customers but also the best-matched soft skillset. The creativity and diligence of our programmers and service professionals allow our customers to quickly convert innovations into realities, meet their milestones, and lead in their market. As a social enterprise corporation, our well-established capacity-building program allows us to competitively provide the scale and speed required by our customers to make their businesses thrive. Some of the many areas we can help you with: • Hardware Design • Embedded Systems • Test Automation • Mobile App Development • Web Development • Media Streaming platforms Development • AI/ML & Data Science • Technical Writing • much more ... Our specialists’ experience and competencies, best business practices, and high-quality infrastructure all allow us to set a new standard for technology development outsourcing that is reliable, innovative, flexible, affordable, scalable, and applicable for companies globally, in any industry sector.
